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Searched refs:mla (Results 1 – 25 of 52) sorted by relevance

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/external/llvm/test/MC/AArch64/
Dneon-mla-mls-instructions.s8 mla v0.8b, v1.8b, v2.8b
9 mla v0.16b, v1.16b, v2.16b
10 mla v0.4h, v1.4h, v2.4h
11 mla v0.8h, v1.8h, v2.8h
12 mla v0.2s, v1.2s, v2.2s
13 mla v0.4s, v1.4s, v2.4s
Dneon-2velem.s9 mla v0.2s, v1.2s, v2.s[2]
10 mla v0.2s, v1.2s, v22.s[2]
11 mla v3.4s, v8.4s, v2.s[1]
12 mla v3.4s, v8.4s, v22.s[3]
19 mla v0.4h, v1.4h, v2.h[2]
20 mla v0.4h, v1.4h, v15.h[2]
21 mla v0.8h, v1.8h, v2.h[7]
22 mla v0.8h, v1.8h, v14.h[6]
Dneon-diagnostics.s114 mla v0.16b, v1.8b, v2.8b
2949 mla v0.2d, v1.2d, v16.d[1]
2950 mla v0.2s, v1.2s, v2.s[4]
2951 mla v0.4s, v1.4s, v2.s[4]
2952 mla v0.2h, v1.2h, v2.h[1]
2953 mla v0.4h, v1.4h, v2.h[8]
2954 mla v0.8h, v1.8h, v2.h[8]
2955 mla v0.4h, v1.4h, v16.h[2]
2956 mla v0.8h, v1.8h, v16.h[2]
Darm64-advsimd.s334 mla.8b v0, v0, v0
405 ; CHECK: mla.8b v0, v0, v0 ; encoding: [0x00,0x94,0x20,0x0e]
1066 mla.4h v0, v0, v0[0]
1067 mla.8h v0, v0, v0[1]
1068 mla.2s v0, v0, v0[2]
1069 mla.4s v0, v0, v0[3]
1135 ; CHECK: mla.4h v0, v0, v0[0] ; encoding: [0x00,0x00,0x40,0x2f]
1136 ; CHECK: mla.8h v0, v0, v0[1] ; encoding: [0x00,0x00,0x50,0x6f]
1137 ; CHECK: mla.2s v0, v0, v0[2] ; encoding: [0x00,0x08,0x80,0x2f]
1138 ; CHECK: mla.4s v0, v0, v0[3] ; encoding: [0x00,0x08,0xa0,0x6f]
/external/libavc/common/armv8/
Dih264_inter_pred_filters_luma_vert_av8.s138 mla v14.8h, v12.8h, v22.8h // temp += temp1 * 20
141 mla v20.8h, v18.8h , v22.8h // temp4 += temp3 * 20
148 mla v16.8h, v12.8h , v22.8h
155 mla v14.8h, v12.8h , v22.8h
162 mla v18.8h, v12.8h , v22.8h
169 mla v16.8h, v12.8h , v22.8h
177 mla v14.8h, v12.8h , v22.8h
183 mla v18.8h, v12.8h , v22.8h
197 mla v14.8h, v12.8h , v22.8h // temp += temp1 * 20
201 mla v20.8h, v18.8h , v22.8h // temp4 += temp3 * 20
[all …]
Dih264_weighted_bi_pred_av8.s177 mla v4.8h, v6.8h , v2.h[2] //weight 2 mult. for rows 1,2
179 mla v8.8h, v10.8h , v2.h[2] //weight 2 mult. for rows 3,4
209 mla v4.8h, v6.8h , v2.h[2] //weight 2 mult. for row 1
213 mla v8.8h, v10.8h , v2.h[2] //weight 2 mult. for row 2
217 mla v12.8h, v14.8h , v2.h[2] //weight 2 mult. for row 3
219 mla v16.8h, v18.8h , v2.h[2] //weight 2 mult. for row 4
255 mla v20.8h, v22.8h , v2.h[2] //weight 2 mult. for row 1L
259 mla v4.8h, v6.8h , v2.h[2] //weight 2 mult. for row 1H
263 mla v24.8h, v26.8h , v2.h[2] //weight 2 mult. for row 2L
267 mla v8.8h, v10.8h , v2.h[2] //weight 2 mult. for row 2H
[all …]
Dih264_inter_pred_luma_vert_qpel_av8.s145 mla v14.8h, v12.8h , v22.8h // temp += temp1 * 20
148 mla v20.8h, v18.8h , v22.8h // temp4 += temp3 * 20
155 mla v16.8h, v12.8h , v22.8h
162 mla v14.8h, v12.8h , v22.8h
171 mla v18.8h, v12.8h , v22.8h
178 mla v16.8h, v12.8h , v22.8h
188 mla v14.8h, v12.8h , v22.8h
194 mla v18.8h, v12.8h , v22.8h
212 mla v14.8h, v12.8h , v22.8h // temp += temp1 * 20
218 mla v20.8h, v18.8h , v22.8h // temp4 += temp3 * 20
[all …]
Dih264_inter_pred_luma_horz_hpel_vert_hpel_av8.s113 mla v18.8h, v20.8h , v28.8h
117 mla v20.8h, v24.8h , v28.8h
123 mla v22.8h, v24.8h , v28.8h
194 mla v18.8h, v20.8h , v28.8h
198 mla v20.8h, v24.8h , v28.8h
204 mla v22.8h, v24.8h , v28.8h
273 mla v18.8h, v20.8h , v28.8h
277 mla v20.8h, v24.8h , v28.8h
283 mla v22.8h, v24.8h , v28.8h
355 mla v18.8h, v20.8h , v28.8h
[all …]
Dih264_inter_pred_luma_horz_hpel_vert_qpel_av8.s166 mla v6.8h, v8.8h , v22.8h
180 mla v8.8h, v10.8h , v22.8h
194 mla v10.8h, v12.8h , v22.8h
208 mla v12.8h, v14.8h , v22.8h
222 mla v14.8h, v16.8h , v22.8h
239 mla v16.8h, v18.8h , v22.8h
267 mla v20.8h, v2.8h , v22.8h
310 mla v8.8h, v2.8h , v22.8h
348 mla v28.8h, v2.8h , v22.8h
414 mla v6.8h, v8.8h , v22.8h
[all …]
Dih264_inter_pred_luma_horz_qpel_vert_hpel_av8.s175 mla v18.8h, v20.8h , v28.8h
179 mla v20.8h, v24.8h , v28.8h
185 mla v22.8h, v24.8h , v28.8h
262 mla v18.8h, v20.8h , v28.8h
266 mla v20.8h, v24.8h , v28.8h
272 mla v22.8h, v24.8h , v28.8h
346 mla v18.8h, v20.8h , v28.8h
350 mla v20.8h, v24.8h , v28.8h
356 mla v22.8h, v24.8h , v28.8h
433 mla v18.8h, v20.8h , v28.8h
[all …]
Dih264_deblk_luma_av8.s367 mla v12.8h, v8.8h , v1.h[0] //(p0+q0+p1)+3*p2+2*p3 L
368 mla v4.8h, v16.8h , v1.h[0] //(p0+q0+p1)+3*p2+2*p3 H
880 mla v24.8h, v20.8h , v28.8h //p2 + X2(p1) + X2(p0) + X2(q0) + q1 L
881 mla v26.8h, v22.8h , v28.8h //p2 + X2(p1) + X2(p0) + X2(q0) + q1 H
956 mla v14.8h, v18.8h , v28.8h //p1 + X2(p0) + X2(q0) + X2(q1) + q2L
958 mla v4.8h, v26.8h , v28.8h //p1 + X2(p0) + X2(q0) + X2(q1) + q2H
991 mla v18.8h, v16.8h , v28.8h //X2(q3) + X3(q2) + q1 + q0 + p0 L
995 mla v26.8h, v4.8h , v28.8h //X2(q3) + X3(q2) + q1 + q0 + p0 H
Dih264_deblk_chroma_av8.s519 mla v14.8h, v18.8h , v28.8h
520 mla v16.8h, v20.8h , v28.8h //4*(q0 - p0) + (p1 - q1)
Dih264_resi_trans_quant_av8.s695 mla v25.4s, v2.4s, v30.4s
696 mla v26.4s, v3.4s, v30.4s
/external/llvm/test/CodeGen/AArch64/
Dneon-mla-mls.ll5 ;CHECK: mla {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
12 ;CHECK: mla {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
19 ;CHECK: mla {{v[0-9]+}}.4h, {{v[0-9]+}}.4h, {{v[0-9]+}}.4h
26 ;CHECK: mla {{v[0-9]+}}.8h, {{v[0-9]+}}.8h, {{v[0-9]+}}.8h
33 ;CHECK: mla {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, {{v[0-9]+}}.2s
40 ;CHECK: mla {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s
Darm64-promote-const.ll47 ; PROMOTED-NEXT: mla.16b v0, v0, v[[REGNUM]]
58 ; REGULAR-NEXT: mla.16b v0, v0, v[[REGNUM]]
Darm64-neon-2velem.ll47 ; CHECK: mla {{v[0-9]+}}.4h, {{v[0-9]+}}.4h, {{v[0-9]+}}.h[3]
58 ; CHECK: mla {{v[0-9]+}}.8h, {{v[0-9]+}}.8h, {{v[0-9]+}}.h[3]
69 ; CHECK: mla {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, {{v[0-9]+}}.s[1]
80 ; CHECK: mla {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.s[1]
91 ; CHECK: mla {{v[0-9]+}}.4h, {{v[0-9]+}}.4h, {{v[0-9]+}}.h[7]
102 ; CHECK: mla {{v[0-9]+}}.8h, {{v[0-9]+}}.8h, {{v[0-9]+}}.h[7]
113 ; CHECK: mla {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, {{v[0-9]+}}.s[3]
124 ; CHECK: mla {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.s[3]
1500 ; CHECK: mla {{v[0-9]+}}.4h, {{v[0-9]+}}.4h, {{v[0-9]+}}.h[0]
1511 ; CHECK: mla {{v[0-9]+}}.8h, {{v[0-9]+}}.8h, {{v[0-9]+}}.h[0]
[all …]
/external/llvm/test/CodeGen/Thumb2/
Dthumb2-mla.ll11 ; CHECK: mla r0, r0, r1, r2
22 ; CHECK: mla r0, r0, r1, r2
Dthumb2-mul.ll16 ; CHECK: mla r0, r2, r0, r1
/external/jpeg/
Darmv6_idct.S111 mla r0, r10, r0, r4
112 mla r6, r11, r6, r2
128 mla r1, r10, r1, r7
129 mla r3, r11, r3, r5
/external/llvm/test/MC/ARM/
Dmul-v4.s14 @ ARMV4: mla r0, r1, r2, r3 @ encoding: [0x91,0x32,0x20,0xe0]
18 mla r0, r1, r2, r3 label
Ddirective-arch-armv4.s33 mla r4, r5, r6, r3
/external/llvm/lib/CodeGen/
DREADME.txt10 mla r4, r3, lr, r4
19 mla r4, r3, lr, r4
27 mla r4, r3, lr, r4
/external/libhevc/common/arm64/
Dihevc_deblk_luma_vert.s234 mla v20.8h, v0.8h, v16.8h
286 mla v26.8h, v0.8h, v16.8h
/external/libhevc/common/arm/
Dihevc_weighted_pred_bi.s159 mla r4,r12,r8,r4 @(lvl_shift1 * wgt0) + (lvl_shift2 * wgt1)
/external/vixl/src/vixl/a64/
Dlogic-a64.cc796 LogicVRegister Simulator::mla(VectorFormat vform, in mla() function in vixl::Simulator
841 LogicVRegister Simulator::mla(VectorFormat vform, in mla() function in vixl::Simulator
848 return mla(vform, dst, src1, dup_element(indexform, temp, src2, index)); in mla()
3164 mla(vform, dst, temp1, temp2); in umlal()
3176 mla(vform, dst, temp1, temp2); in umlal2()
3188 mla(vform, dst, temp1, temp2); in smlal()
3200 mla(vform, dst, temp1, temp2); in smlal2()

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