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/external/llvm/test/MC/AArch64/
Dtls-relocs.s6 movz x1, #:dtprel_g2:var
8 movz x3, #:dtprel_g2:var
28 movz x5, #:dtprel_g1:var
30 movz w7, #:dtprel_g1:var
60 movz x11, #:dtprel_g0:var
62 movz w13, #:dtprel_g0:var
177 movz x15, #:gottprel_g1:var
178 movz w14, #:gottprel_g1:var
218 movz x3, #:tprel_g2:var
230 movz x5, #:tprel_g1:var
[all …]
Delf-reloc-movw.s4 movz x0, #:abs_g0:some_label
7 movz x3, #:abs_g1:some_label
10 movz x3, #:abs_g2:some_label
13 movz x7, #:abs_g3:some_label
16 movz x13, #:abs_g0_s:some_label
19 movz x19, #:abs_g1_s:some_label
22 movz x19, #:abs_g2_s:some_label
Darm64-tls-relocs.s10 movz x15, #:gottprel_g1:var
43 movz x3, #:tprel_g2:var
54 movz x5, #:tprel_g1:var
56 movz w7, #:tprel_g1:var
80 movz x11, #:tprel_g0:var
82 movz w13, #:tprel_g0:var
167 movz x3, #:dtprel_g2:var
178 movz x5, #:dtprel_g1:var
180 movz w7, #:dtprel_g1:var
204 movz x11, #:dtprel_g0:var
[all …]
Darm64-large-relocs.s4 movz x2, #:abs_g0:sym
14 movz x4, #:abs_g1:sym
24 movz x6, #:abs_g2:sym
34 movz x8, #:abs_g3:sym
Djump-table.s19 movz x0, #1
25 movz x0, #2
28 movz x0, #4
31 movz x0, #8
/external/boringssl/src/crypto/aes/asm/
Daes-586.pl253 &movz ($s[2],&HB($s[0]));
258 &movz ($s[1],&HB($v1));
266 &movz ($v0,&HB($v1));
269 &movz ($v0,&HB($v1));
278 &movz ($v1,&HB($v0));
281 &movz ($v1,&HB($v0));
290 &movz ($v0,&HB($v1));
293 &movz ($v0,&HB($v1));
305 &movz ($v0,&LB($s0)); # 3, 2, 1, 0*
308 &movz ($v0,&HB($s1)); # 7, 6, 5*, 4
[all …]
/external/llvm/test/CodeGen/AArch64/
Darm64-code-model-large-abs.ll11 ; The movz/movk calculation should end up returned directly in x0.
12 ; CHECK: movz x0, #:abs_g3:var8
23 ; CHECK: movz x[[ADDR_REG:[0-9]+]], #:abs_g3:var8
34 ; CHECK: movz x[[ADDR_REG:[0-9]+]], #:abs_g3:var16
45 ; CHECK: movz x[[ADDR_REG:[0-9]+]], #:abs_g3:var32
56 ; CHECK: movz x[[ADDR_REG:[0-9]+]], #:abs_g3:var64
67 ; CHECK: movz x[[ADDR_REG:[0-9]+]], #:abs_g3:[[CPADDR:.LCPI[0-9]+_[0-9]+]]
Dcode-model-large-abs.ll11 ; The movz/movk calculation should end up returned directly in x0.
12 ; CHECK: movz x0, #:abs_g3:var8
23 ; CHECK: movz x[[ADDR_REG:[0-9]+]], #:abs_g3:var8
34 ; CHECK: movz x[[ADDR_REG:[0-9]+]], #:abs_g3:var16
45 ; CHECK: movz x[[ADDR_REG:[0-9]+]], #:abs_g3:var32
56 ; CHECK: movz x[[ADDR_REG:[0-9]+]], #:abs_g3:var64
Darm64-zero-cycle-zeroing.ll21 ; CHECK: movz w0, #0
22 ; CHECK: movz w1, #0
31 ; CHECK: movz x0, #0
32 ; CHECK: movz x1, #0
Darm64-patchpoint-webkit_jscc.ll13 ; CHECK-NEXT: movz x16, #0xffff, lsl #32
21 ; FAST-NEXT: movz x16, #0xffff, lsl #32
44 ; CHECK-NEXT: movz x16, #0xffff, lsl #32
57 ; FAST-NEXT: movz x16, #0xffff, lsl #32
71 ; CHECK: movz w[[REG:[0-9]+]], #0xa
82 ; CHECK-NEXT: movz x16, #0xffff, lsl #32
92 ; FAST-NEXT: movz [[REG5:x[0-9]+]], #0xa
99 ; FAST-NEXT: movz x16, #0xffff, lsl #32
Darm64-movi.ll46 define i32 @movz() nounwind {
47 ; CHECK-LABEL: movz:
48 ; CHECK: movz w0, #0x5
54 ; CHECK: movz x0, #0x5, lsl #48
63 ; CHECK: movz x0, #0x5, lsl #32
70 ; CHECK: movz x0, #0x8654, lsl #32
198 ; CHECK: movz x0, #0xffff, lsl #48
Darm64-fast-isel-addr-offset.ll12 ; CHECK: movz x[[REG2:[0-9]+]], #0x4e20
25 ; CHECK: movz x[[REG2:[0-9]+]], #0x9c40
40 ; CHECK: movz x[[REG:[0-9]+]], #0xb3a, lsl #32
Di128-align.ll16 ; CHECK: {{movz x0, #48|orr w0, wzr, #0x30}}
28 ; CHECK: {{movz x0, #16|orr w0, wzr, #0x10}}
Dextern-weak.ll24 ; CHECK-LARGE: movz x0, #:abs_g3:var
50 ; CHECK-LARGE: movz [[ADDR:x[0-9]+]], #:abs_g3:arr_var
67 ; CHECK-LARGE: movz x0, #:abs_g3:defined_weak_var
Darm64-extern-weak.ll23 ; CHECK-LARGE: movz x0, #:abs_g3:var
46 ; CHECK-LARGE: movz [[ARR_VAR:x[0-9]+]], #:abs_g3:arr_var
62 ; CHECK-LARGE: movz x0, #:abs_g3:defined_weak_var
/external/valgrind/none/tests/mips32/
DMoveIns.stdout.exp-BE306 movz.s $f0, $f2, $t3 :: fs rt 0x0
307 movz.s $f0, $f2, $t3 :: fs rt 0x0
308 movz.s $f0, $f2, $t3 :: fs rt 0x0
309 movz.s $f0, $f2, $t3 :: fs rt 0x0
310 movz.s $f0, $f2, $t3 :: fs rt 0x0
311 movz.s $f0, $f2, $t3 :: fs rt 0xc0e96d19
312 movz.s $f0, $f2, $t3 :: fs rt 0x4e6e6b28
313 movz.s $f0, $f2, $t3 :: fs rt 0x4e6e6b28
314 movz.s $f0, $f2, $t3 :: fs rt 0x0
315 movz.s $f0, $f2, $t3 :: fs rt 0x0
[all …]
/external/llvm/test/CodeGen/X86/
Dmasked-iv-safe.ll7 ; CHECK-NOT: {{and|movz|sar|shl}}
9 ; CHECK-NOT: {{and|movz|sar|shl}}
40 ; CHECK-NOT: {{and|movz|sar|shl}}
42 ; CHECK-NOT: {{and|movz|sar|shl}}
73 ; CHECK-NOT: {{and|movz|sar|shl}}
75 ; CHECK-NOT: {{and|movz|sar|shl}}
108 ; CHECK-NOT: {{and|movz|sar|shl}}
110 ; CHECK-NOT: {{and|movz|sar|shl}}
143 ; CHECK-NOT: {{and|movz|sar|shl}}
145 ; CHECK-NOT: {{and|movz|sar|shl}}
[all …]
/external/llvm/lib/Target/X86/
DX86InstrExtension.td70 "movz{bw|x}\t{$src, $dst|$dst, $src}", [], IIC_MOVZX_R16_R8>,
74 "movz{bw|x}\t{$src, $dst|$dst, $src}", [], IIC_MOVZX_R16_M8>,
78 "movz{bl|x}\t{$src, $dst|$dst, $src}",
82 "movz{bl|x}\t{$src, $dst|$dst, $src}",
86 "movz{wl|x}\t{$src, $dst|$dst, $src}",
90 "movz{wl|x}\t{$src, $dst|$dst, $src}",
100 "movz{bl|x}\t{$src, $dst|$dst, $src} # NOREX",
105 "movz{bl|x}\t{$src, $dst|$dst, $src} # NOREX",
150 "movz{bq|x}\t{$src, $dst|$dst, $src}", [], IIC_MOVZX>,
153 "movz{bq|x}\t{$src, $dst|$dst, $src}", [], IIC_MOVZX>,
[all …]
/external/llvm/test/MC/Mips/
Dmicromips-movcond-instructions.s12 # CHECK-EL: movz $9, $6, $7 # encoding: [0xe6,0x00,0x58,0x48]
19 # CHECK-EB: movz $9, $6, $7 # encoding: [0x00,0xe6,0x48,0x58]
23 movz $9, $6, $7
/external/llvm/test/CodeGen/Mips/
Dzeroreg.ll38 ; 32-CMOV: movz $2, $zero, $4
44 ; 64-CMOV: movz $2, $zero, $4
90 ; 32-CMOV-DAG: movz $[[R0]], $zero, $4
91 ; 32-CMOV-DAG: movz $[[R1]], $zero, $4
100 ; 64-CMOV: movz $2, $zero, $4
Dcmov.ll97 ; 32-CMOV: movz ${{[26]}}, $5, $[[R0]]
105 ; 64-CMOV: movz ${{[26]}}, $5, $[[R0]]
161 ; 32-CMOV-DAG: movz $[[R1]], $6, $[[R0]]
162 ; 32-CMOV-DAG: movz $[[R2]], $7, $[[R0]]
175 ; 64-CMOV: movz ${{[26]}}, $5, $[[R0]]
235 ; (movz t, (setlt a, N + 1), f)
243 ; 32-CMOV-DAG: movz $[[I5]], $[[I3]], $[[R0]]
256 ; 64-CMOV-DAG: movz $[[I5]], $[[I3]], $[[R0]]
317 ; 32-CMOV-DAG: movz $[[I5]], $[[I3]], $[[R0]]
330 ; 64-CMOV-DAG: movz $[[I5]], $[[I3]], $[[R0]]
[all …]
/external/boringssl/src/crypto/rc4/asm/
Drc4-586.pl138 &movz ($xx,&LB($xx)); # (*)
139 &movz ($ty,&LB($ty)); # (*)
274 &movz ($tx,&BP(0,$dat,$xx));
278 &movz ($ty,&BP(0,$dat,$yy));
282 &movz ($ty,&BP(0,$dat,$ty));
286 &movz ($tx,&BP(0,$dat,$xx));
/external/llvm/lib/Target/Mips/
DMipsCondMov.td106 def MOVZ_I_I : MMRel, CMov_I_I_FT<"movz", GPR32Opnd, GPR32Opnd, II_MOVZ>,
110 def MOVZ_I_I64 : CMov_I_I_FT<"movz", GPR32Opnd, GPR64Opnd, II_MOVZ>,
112 def MOVZ_I64_I : CMov_I_I_FT<"movz", GPR64Opnd, GPR32Opnd, II_MOVZ>,
114 def MOVZ_I64_I64 : CMov_I_I_FT<"movz", GPR64Opnd, GPR64Opnd, II_MOVZ>,
130 def MOVZ_I_S : MMRel, CMov_I_F_FT<"movz.s", GPR32Opnd, FGR32Opnd, II_MOVZ_S>,
134 def MOVZ_I64_S : CMov_I_F_FT<"movz.s", GPR64Opnd, FGR32Opnd, II_MOVZ_S>,
146 def MOVZ_I_D32 : MMRel, CMov_I_F_FT<"movz.d", GPR32Opnd, AFGR64Opnd,
154 def MOVZ_I_D64 : CMov_I_F_FT<"movz.d", GPR32Opnd, FGR64Opnd, II_MOVZ_D>,
159 def MOVZ_I64_D64 : CMov_I_F_FT<"movz.d", GPR64Opnd, FGR64Opnd, II_MOVZ_D>,
/external/llvm/test/MC/Mips/mips3/
Dinvalid-mips4.s26 …movz $a1,$s6,$9 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU featur…
27 …movz.d $f12,$f29,$9 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU featur…
28 …movz.s $f25,$f7,$v1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU featur…
/external/llvm/test/MC/Mips/mips32r6/
Dinvalid-mips32.s23 …movz $a1,$s6,$9 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU fe…
24 …movz.d $f12,$f29,$9 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU fe…
25 …movz.s $f25,$f7,$v1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU fe…

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