| /external/llvm/test/CodeGen/ARM/ |
| D | intrinsics.ll | 10 ; CHECK: mrc2
11 %1 = tail call i32 @llvm.arm.mrc2(i32 7, i32 1, i32 1, i32 1, i32 4) nounwind
35 declare i32 @llvm.arm.mrc2(i32, i32, i32, i32, i32) nounwind
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| /external/llvm/test/MC/Disassembler/ARM/ |
| D | invalid-armv8.txt | 64 # CHECK-V7: mrc2
69 # CHECK-V7: mrc2
74 # CHECK-V7: mrc2
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| D | invalid-thumbv8.txt | 64 # CHECK-V7: mrc2
69 # CHECK-V7: mrc2
74 # CHECK-V7: mrc2
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| D | basic-arm-instructions.txt | 816 # CHECK: mrc2 p14, #0, r1, c1, c2, #4
817 # CHECK: mrc2 p9, #7, apsr_nzcv, c15, c0, #1
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| D | thumb2.txt | 1089 # CHECK: mrc2 p14, #0, r1, c1, c2, #4
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| /external/llvm/test/MC/ARM/ |
| D | thumb2-diagnostics.s | 35 mrc2 p14, #8, r1, c1, c2, #4
36 mrc2 p14, #0, r1, c1, c2, #9
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| D | diagnostics.s | 177 mrc2 p14, #8, r1, c1, c2, #4
178 mrc2 p14, #0, r1, c1, c2, #9
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| D | basic-thumb2-instructions.s | 1449 mrc2 p12, #3, r3, c3, c4
1450 mrc2 p14, #0, r1, c1, c2, #4
1451 mrc2 p8, #7, apsr_nzcv, c15, c0, #1
1456 @ CHECK: mrc2 p12, #3, r3, c3, c4, #0 @ encoding: [0x73,0xfe,0x14,0x3c]
1457 @ CHECK: mrc2 p14, #0, r1, c1, c2, #4 @ encoding: [0x11,0xfe,0x92,0x1e]
1458 @ CHECK: mrc2 p8, #7, apsr_nzcv, c15, c0, #1 @ encoding: [0xff,0xfe,0x30,0xf8]
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| D | basic-arm-instructions.s | 1373 mrc2 p14, #0, r1, c1, c2, #4
1374 mrc2 p9, #7, apsr_nzcv, c15, c0, #1
1378 @ CHECK: mrc2 p14, #0, r1, c1, c2, #4 @ encoding: [0x92,0x1e,0x11,0xfe]
1379 @ CHECK: mrc2 p9, #7, apsr_nzcv, c15, c0, #1 @ encoding: [0x30,0xf9,0xff,0xfe]
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| /external/v8/src/arm/ |
| D | assembler-arm.h | 1092 void mrc2(Coprocessor coproc, int opcode_1,
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| D | assembler-arm.cc | 2098 void Assembler::mrc2(Coprocessor coproc, in mrc2() function in v8::internal::Assembler
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| /external/llvm/lib/Target/ARM/ |
| D | ARMInstrThumb2.td | 4194 def t2MRC2 : t2MovRCopro<0b1111, "mrc2", 1,
4199 def : t2InstAlias<"mrc2${p} $cop, $opc1, $Rt, $CRn, $CRm",
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| D | ARMInstrInfo.td | 5025 def MRC2 : MovRCopro2<"mrc2", 1 /* from coprocessor to ARM core register */,
5030 def : ARMInstAlias<"mrc2 $cop, $opc1, $Rt, $CRn, $CRm",
|