Searched refs:num_banks (Results 1 – 7 of 7) sorted by relevance
98 uint32_t num_banks; member235 surf_man->hw_info.num_banks = 4; in r6_init_hw_info()238 surf_man->hw_info.num_banks = 8; in r6_init_hw_info()241 surf_man->hw_info.num_banks = 8; in r6_init_hw_info()366 xalign = (surf_man->hw_info.group_bytes * surf_man->hw_info.num_banks) / in r6_surface_init_2d()368 xalign = MAX2(tilew * surf_man->hw_info.num_banks, xalign); in r6_surface_init_2d()378 surf_man->hw_info.num_banks * in r6_surface_init_2d()520 surf_man->hw_info.num_banks = 4; in eg_init_hw_info()523 surf_man->hw_info.num_banks = 8; in eg_init_hw_info()526 surf_man->hw_info.num_banks = 16; in eg_init_hw_info()[all …]
63 int num_banks; member89 info->num_banks) * 8; in radeon_get_pitch_align()91 pitch_align = MAX(info->num_banks * 8, pitch_align); in radeon_get_pitch_align()154 base_align = MAX(info->num_banks * info->num_channels * 8 * 8 * bpe, in radeon_get_base_align()368 info->num_banks = 4; in radeon_init_tile_config()371 info->num_banks = 8; in radeon_init_tile_config()374 info->num_banks = 16; in radeon_init_tile_config()414 info->num_banks = 4; in radeon_init_tile_config()417 info->num_banks = 8; in radeon_init_tile_config()
796 rscreen->tiling_info.num_banks = 4; in r600_interpret_tiling()799 rscreen->tiling_info.num_banks = 8; in r600_interpret_tiling()839 rscreen->tiling_info.num_banks = 4; in evergreen_interpret_tiling()842 rscreen->tiling_info.num_banks = 8; in evergreen_interpret_tiling()845 rscreen->tiling_info.num_banks = 16; in evergreen_interpret_tiling()
77 unsigned num_banks; member
1065 nbanks = eg_num_banks(rscreen->tiling_info.num_banks); in evergreen_create_sampler_view()1307 nbanks = eg_num_banks(rscreen->tiling_info.num_banks); in evergreen_init_color_surface()1473 nbanks = eg_num_banks(rscreen->tiling_info.num_banks); in evergreen_init_depth_surface()
56 unsigned num_banks; member
610 rscreen->tiling_info.num_banks = 4; in evergreen_interpret_tiling()613 rscreen->tiling_info.num_banks = 8; in evergreen_interpret_tiling()616 rscreen->tiling_info.num_banks = 16; in evergreen_interpret_tiling()