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/external/llvm/test/CodeGen/NVPTX/
Dfma-disable.ll1 ; RUN: llc < %s -march=nvptx -mcpu=sm_20 -nvptx-fma-level=1 | FileCheck %s -check-prefix=FMA
2 ; RUN: llc < %s -march=nvptx -mcpu=sm_20 -nvptx-fma-level=0 | FileCheck %s -check-prefix=MUL
3 ; RUN: llc < %s -march=nvptx64 -mcpu=sm_20 -nvptx-fma-level=1 | FileCheck %s -check-prefix=FMA
4 ; RUN: llc < %s -march=nvptx64 -mcpu=sm_20 -nvptx-fma-level=0 | FileCheck %s -check-prefix=MUL
Drsqrt.ll1 ; RUN: llc < %s -march=nvptx -mcpu=sm_20 -nvptx-prec-divf32=1 -nvptx-prec-sqrtf32=0 | FileCheck %s
Ddiv-ri.ll1 ; RUN: llc < %s -march=nvptx -mcpu=sm_20 -nvptx-prec-divf32=0 | FileCheck %s
Dcallchain.ll1 ; RUN: llc < %s -march=nvptx -mcpu=sm_20 | FileCheck %s
3 target triple = "nvptx"
Dconstant-vectors.ll1 ; RUN: llc < %s -march=nvptx -mcpu=sm_20 | FileCheck %s
3 target triple = "nvptx-nvidia-cuda"
Dvector-call.ll1 ; RUN: llc < %s -march=nvptx -mcpu=sm_20 | FileCheck %s
3 target triple = "nvptx-unknown-cuda"
Dvec8.ll1 ; RUN: llc < %s -march=nvptx -mcpu=sm_20 | FileCheck %s
3 target triple = "nvptx-unknown-cuda"
Dsurf-write-cuda.ll1 ; RUN: llc < %s -march=nvptx -mcpu=sm_20 | FileCheck %s --check-prefix=SM20
2 ; RUN: llc < %s -march=nvptx -mcpu=sm_30 | FileCheck %s --check-prefix=SM30
4 target triple = "nvptx-unknown-cuda"
Dload-sext-i1.ll1 ; RUN: llc < %s -march=nvptx -mcpu=sm_20 | FileCheck %s
4 target triple = "nvptx-nvidia-cuda"
Dnvcl-param-align.ll1 ; RUN: llc < %s -march=nvptx -mcpu=sm_20 | FileCheck %s
3 target triple = "nvptx-unknown-nvcl"
Di1-global.ll1 ; RUN: llc < %s -march=nvptx -mcpu=sm_20 | FileCheck %s
4 target triple = "nvptx-nvidia-cuda"
Di1-param.ll1 ; RUN: llc < %s -march=nvptx -mcpu=sm_20 | FileCheck %s
4 target triple = "nvptx-nvidia-cuda"
Dsurf-write.ll1 ; RUN: llc < %s -march=nvptx -mcpu=sm_20 | FileCheck %s
3 target triple = "nvptx-unknown-nvcl"
Dgeneric-to-nvvm.ll1 ; RUN: llc < %s -march=nvptx -mcpu=sm_20 | FileCheck %s
4 target triple = "nvptx-nvidia-cuda"
Dsurf-read.ll1 ; RUN: llc < %s -march=nvptx -mcpu=sm_20 | FileCheck %s
3 target triple = "nvptx-unknown-nvcl"
Dsurf-read-cuda.ll1 ; RUN: llc < %s -march=nvptx -mcpu=sm_20 | FileCheck %s --check-prefix=SM20
2 ; RUN: llc < %s -march=nvptx -mcpu=sm_30 | FileCheck %s --check-prefix=SM30
4 target triple = "nvptx-unknown-cuda"
Dtex-read-cuda.ll1 ; RUN: llc < %s -march=nvptx -mcpu=sm_20 | FileCheck %s --check-prefix=SM20
2 ; RUN: llc < %s -march=nvptx -mcpu=sm_30 | FileCheck %s --check-prefix=SM30
5 target triple = "nvptx-unknown-cuda"
Dtex-read.ll1 ; RUN: llc < %s -march=nvptx -mcpu=sm_20 | FileCheck %s
3 target triple = "nvptx-unknown-nvcl"
Dfast-math.ll1 ; RUN: llc < %s -march=nvptx -mcpu=sm_20 | FileCheck %s
43 attributes #1 = { "nvptx-f32ftz" = "true" }
Daddrspacecast.ll1 ; RUN: llc < %s -march=nvptx -mcpu=sm_20 -disable-nvptx-favor-non-generic | FileCheck %s -check-pre…
2 ; RUN: llc < %s -march=nvptx64 -mcpu=sm_20 -disable-nvptx-favor-non-generic | FileCheck %s -check-p…
Drefl1.ll1 ; RUN: llc < %s -march=nvptx -mcpu=sm_20 | FileCheck %s
3 target triple = "nvptx-nvidia-cuda"
Dtexsurf-queries.ll1 ; RUN: llc < %s -march=nvptx -mcpu=sm_20 | FileCheck %s --check-prefix=SM20
2 ; RUN: llc < %s -march=nvptx -mcpu=sm_30 | FileCheck %s --check-prefix=SM30
4 target triple = "nvptx-unknown-cuda"
Daccess-non-generic.ll1 ; RUN: llc < %s -march=nvptx -mcpu=sm_20 | FileCheck %s --check-prefix PTX
3 ; RUN: opt < %s -S -nvptx-favor-non-generic -dce | FileCheck %s --check-prefix IR
8 ; Verifies nvptx-favor-non-generic correctly optimizes generic address space
Drotate.ll1 ; RUN: llc < %s -march=nvptx -mcpu=sm_20 | FileCheck --check-prefix=SM20 %s
2 ; RUN: llc < %s -march=nvptx -mcpu=sm_35 | FileCheck --check-prefix=SM35 %s
Dtuple-literal.ll1 ; RUN: llc < %s -march=nvptx -mcpu=sm_20

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