| /external/valgrind/none/tests/arm/ |
| D | v6intThumb.c | 711 TESTINST4("add r0, r1, r2, lsl r3", 0, 0xffffffff, 0, r0, r1, r2, r3, cv); in old_main()
712 TESTINST4("add r0, r1, r2, lsl r3", 0, 0xffffffff, 1, r0, r1, r2, r3, cv); in old_main()
713 TESTINST4("add r0, r1, r2, lsl r3", 0, 0xffffffff, 31, r0, r1, r2, r3, cv); in old_main()
714 TESTINST4("add r0, r1, r2, lsl r3", 0, 0xffffffff, 32, r0, r1, r2, r3, cv); in old_main()
715 TESTINST4("add r0, r1, r2, lsl r3", 0, 0xffffffff, 255, r0, r1, r2, r3, cv); in old_main()
716 TESTINST4("add r0, r1, r2, lsl r3", 0, 0xffffffff, 256, r0, r1, r2, r3, cv); in old_main()
717 TESTINST4("add r0, r1, r2, lsr r3", 0, 0xffffffff, 0, r0, r1, r2, r3, cv); in old_main()
718 TESTINST4("add r0, r1, r2, lsr r3", 0, 0xffffffff, 1, r0, r1, r2, r3, cv); in old_main()
719 TESTINST4("add r0, r1, r2, lsr r3", 0, 0xffffffff, 31, r0, r1, r2, r3, cv); in old_main()
720 TESTINST4("add r0, r1, r2, lsr r3", 0, 0xffffffff, 32, r0, r1, r2, r3, cv); in old_main()
[all …]
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| D | v6intARM.c | 425 TESTINST4("add r0, r1, r2, lsl r3", 0, 0xffffffff, 0, r0, r1, r2, r3, c); in main()
426 TESTINST4("add r0, r1, r2, lsl r3", 0, 0xffffffff, 1, r0, r1, r2, r3, c); in main()
427 TESTINST4("add r0, r1, r2, lsl r3", 0, 0xffffffff, 31, r0, r1, r2, r3, c); in main()
428 TESTINST4("add r0, r1, r2, lsl r3", 0, 0xffffffff, 32, r0, r1, r2, r3, c); in main()
429 TESTINST4("add r0, r1, r2, lsl r3", 0, 0xffffffff, 255, r0, r1, r2, r3, c); in main()
430 TESTINST4("add r0, r1, r2, lsl r3", 0, 0xffffffff, 256, r0, r1, r2, r3, c); in main()
431 TESTINST4("add r0, r1, r2, lsr r3", 0, 0xffffffff, 0, r0, r1, r2, r3, c); in main()
432 TESTINST4("add r0, r1, r2, lsr r3", 0, 0xffffffff, 1, r0, r1, r2, r3, c); in main()
433 TESTINST4("add r0, r1, r2, lsr r3", 0, 0xffffffff, 31, r0, r1, r2, r3, c); in main()
434 TESTINST4("add r0, r1, r2, lsr r3", 0, 0xffffffff, 32, r0, r1, r2, r3, c); in main()
[all …]
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| D | v6media.c | 170 TESTINST4("mla r0, r1, r2, r3", 0, 0, 1, r0, r1, r2, r3, 0); in main()
171 TESTINST4("mla r0, r1, r2, r3", 0xffffffff, 0, 1, r0, r1, r2, r3, 0); in main()
172 TESTINST4("mla r0, r1, r2, r3", 0, 0xffffffff, 1, r0, r1, r2, r3, 0); in main()
173 TESTINST4("mla r0, r1, r2, r3", 0xffffffff, 0xffffffff, 1, r0, r1, r2, r3, 0); in main()
174 TESTINST4("mla r0, r1, r2, r3", 0x7fffffff, 0x7fffffff, 1, r0, r1, r2, r3, 0); in main()
175 TESTINST4("mla r0, r1, r2, r3", 0x0000ffff, 0x0000ffff, 1, r0, r1, r2, r3, 0); in main()
179 TESTINST4("mlas r0, r1, r2, r3", 0, 0, 1, r0, r1, r2, r3, 0); in main()
180 TESTINST4("mlas r0, r1, r2, r3", 0xffffffff, 0, 1, r0, r1, r2, r3, 0); in main()
181 TESTINST4("mlas r0, r1, r2, r3", 0, 0xffffffff, 1, r0, r1, r2, r3, 0); in main()
182 TESTINST4("mlas r0, r1, r2, r3", 0xffffffff, 0xffffffff, 1, r0, r1, r2, r3, 0); in main()
[all …]
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| /external/boringssl/src/crypto/chacha/ |
| D | chacha_vec_arm.S | 65 mov r8, r3
81 ldmia r4, {r0, r1, r2, r3}
90 stmia r4, {r0, r1, r2, r3}
95 ldr r3, [r7, #84]
102 vldr d24, [r3, #64]
103 vldr d25, [r3, #72]
104 ldr r3, [lr, #12] @ unaligned
106 stmia r5!, {r0, r1, r2, r3}
114 ldr r3, [lr, #12] @ unaligned
116 stmia r6!, {r0, r1, r2, r3}
[all …]
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| /external/llvm/test/MC/ARM/ |
| D | arm-arithmetic-aliases.s | 8 sub r2, r2, r3
9 sub r2, r3
13 @ CHECK: sub r2, r2, r3 @ encoding: [0x03,0x20,0x42,0xe0]
14 @ CHECK: sub r2, r2, r3 @ encoding: [0x03,0x20,0x42,0xe0]
18 add r2, r2, r3
19 add r2, r3
23 @ CHECK: add r2, r2, r3 @ encoding: [0x03,0x20,0x82,0xe0]
24 @ CHECK: add r2, r2, r3 @ encoding: [0x03,0x20,0x82,0xe0]
28 and r2, r2, r3
29 and r2, r3
[all …]
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| D | basic-thumb-instructions.s | 48 adds r1, r2, r3
51 @ CHECK: adds r1, r2, r3 @ encoding: [0xd1,0x18]
78 add sp, r3
81 @ CHECK: add sp, r3 @ encoding: [0x9d,0x44]
91 adr r3, #1020
99 @ CHECK: adr r3, #1020 @ encoding: [0xff,0xa3]
104 asrs r2, r3, #32
105 asrs r2, r3, #5
106 asrs r2, r3, #1
109 asrs r3, r5, #21
[all …]
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| D | arm-ldrd.s | 6 ldrd r1, r2, [r3, #4]
7 ldrd r1, r2, [r3], #4
8 ldrd r1, r2, [r3, #4]!
9 ldrd r1, r2, [r3, -r4]!
10 ldrd r1, r2, [r3, r4]
11 ldrd r1, r2, [r3], r4
20 ldrd r0, r3, [pc, #0]
21 ldrd r0, r3, [r4, #4]
22 ldrd r0, r3, [r4], #4
23 ldrd r0, r3, [r4, #4]!
[all …]
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| D | mul-v4.s | 14 @ ARMV4: mla r0, r1, r2, r3 @ encoding: [0x91,0x32,0x20,0xe0]
15 @ ARMV4: mlas r0, r1, r2, r3 @ encoding: [0x91,0x32,0x30,0xe0]
16 @ ARMV4: mlane r0, r1, r2, r3 @ encoding: [0x91,0x32,0x20,0x10]
17 @ ARMV4: mlaseq r0, r1, r2, r3 @ encoding: [0x91,0x32,0x30,0x00]
18 mla r0, r1, r2, r3
19 mlas r0, r1, r2, r3
20 mlane r0, r1, r2, r3
21 mlaseq r0, r1, r2, r3
23 @ ARMV4: smlal r2, r3, r0, r1 @ encoding: [0x90,0x21,0xe3,0xe0]
24 @ ARMV4: smlals r2, r3, r0, r1 @ encoding: [0x90,0x21,0xf3,0xe0]
[all …]
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| D | arm_instructions.s | 22 @ CHECK: and r1, r2, r3 @ encoding: [0x03,0x10,0x02,0xe0]
23 and r1,r2,r3
25 @ CHECK: ands r1, r2, r3 @ encoding: [0x03,0x10,0x12,0xe0]
26 ands r1,r2,r3
28 @ CHECK: eor r1, r2, r3 @ encoding: [0x03,0x10,0x22,0xe0]
29 eor r1,r2,r3
31 @ CHECK: eors r1, r2, r3 @ encoding: [0x03,0x10,0x32,0xe0]
32 eors r1,r2,r3
34 @ CHECK: sub r1, r2, r3 @ encoding: [0x03,0x10,0x42,0xe0]
35 sub r1,r2,r3
[all …]
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| D | basic-thumb2-instructions.s | 24 adc r3, r7, #0x00550055
27 adc r5, r3, #0x87000000
34 @ CHECK: adc r3, r7, #5570645 @ encoding: [0x47,0xf1,0x55,0x13]
37 @ CHECK: adc r5, r3, #2264924160 @ encoding: [0x43,0xf1,0x07,0x45]
46 adc.w r9, r1, r3
47 adcs.w r9, r1, r3
48 adc r0, r1, r3, ror #4
49 adcs r0, r1, r3, lsl #7
50 adc.w r0, r1, r3, lsr #31
51 adcs.w r0, r1, r3, asr #32
[all …]
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| /external/libhevc/common/arm/ |
| D | ihevc_intra_pred_luma_horz.s | 85 @r3 => dst_strd
125 vst1.8 {q1},[r2],r3 @store in 1st row 0-16 columns
126 vst1.8 {q1},[r9],r3 @store in 1st row 16-32 columns
129 vst1.8 {q2},[r2],r3
130 vst1.8 {q2},[r9],r3
133 vst1.8 {q3},[r2],r3
134 vst1.8 {q3},[r9],r3
137 vst1.8 {q4},[r2],r3
138 vst1.8 {q4},[r9],r3
141 vst1.8 {q1},[r2],r3
[all …]
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| D | ihevc_intra_pred_chroma_horz.s | 85 @r3 => dst_strd
127 vst1.16 {q1},[r2],r3 @store in 1st row 0-16 columns
128 vst1.16 {q1},[r9],r3 @store in 1st row 16-32 columns
131 vst1.16 {q2},[r2],r3
132 vst1.16 {q2},[r9],r3
135 vst1.16 {q3},[r2],r3
136 vst1.16 {q3},[r9],r3
139 vst1.16 {q4},[r2],r3
140 vst1.16 {q4},[r9],r3
143 vst1.16 {q1},[r2],r3
[all …]
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| D | ihevc_intra_pred_luma_mode_18_34.s | 88 @r3 => dst_strd
157 vst1.8 {d0},[r10],r3
158 vst1.8 {d1},[r10],r3
160 vst1.8 {d2},[r10],r3
162 vst1.8 {d3},[r10],r3
165 vst1.8 {d4},[r10],r3
167 vst1.8 {d5},[r10],r3
169 vst1.8 {d6},[r10],r3
171 vst1.8 {d7},[r10],r3
195 vst1.8 {d0},[r10],r3
[all …]
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| /external/libcxxabi/src/Unwind/ |
| D | UnwindRegistersRestore.S | 103 ; thread_state pointer is in r3
109 lwz r2, 16(r3)
110 ; skip r3 for now
113 lwz r6, 32(r3)
114 lwz r7, 36(r3)
115 lwz r8, 40(r3)
116 lwz r9, 44(r3)
117 lwz r10, 48(r3)
118 lwz r11, 52(r3)
119 lwz r12, 56(r3)
[all …]
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| D | UnwindRegistersSave.S | 96 ; thread_state pointer is in r3
99 stw r0, 8(r3)
101 stw r0, 0(r3) ; store lr as ssr0
102 stw r1, 12(r3)
103 stw r2, 16(r3)
104 stw r3, 20(r3)
105 stw r4, 24(r3)
106 stw r5, 28(r3)
107 stw r6, 32(r3)
108 stw r7, 36(r3)
[all …]
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| /external/libvpx/libvpx/vp8/common/ppc/ |
| D | platform_altivec.asm | 25 ;# r3 context_ptr
28 W v20, r3
29 W v21, r3
30 W v22, r3
31 W v23, r3
32 W v24, r3
33 W v25, r3
34 W v26, r3
35 W v27, r3
36 W v28, r3
[all …]
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| D | variance_altivec.asm | 75 load_aligned_16 v4, r3, r10
79 add r3, r3, r4
90 lwz r3, 12(r1)
96 stw r3, 0(r8) ;# sum
100 mullw r3, r3, r3 ;# sum*sum
101 srlwi r3, r3, \DS ;# (sum*sum) >> DS
102 subf r3, r3, r4 ;# sse - ((sum*sum) >> DS)
108 load_aligned_16 v4, r3, r10
112 add r3, r3, r4
116 load_aligned_16 v6, r3, r10
[all …]
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| /external/compiler-rt/lib/builtins/arm/ |
| D | udivmodsi4.S | 38 mov r3, r0
39 udiv r0, r3, r1
40 mls r1, r0, r1, r3
67 clz r3, r1
69 sub r3, r3, ip
72 sub ip, ip, r3, lsl #1
76 sub ip, ip, r3, lsl #2
77 sub ip, ip, r3, lsl #3
78 mov r3, #0
89 lsr r3, r4, #16
[all …]
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| D | udivsi3.S | 67 clz r3, r1
69 sub r3, r3, ip
72 sub ip, ip, r3, lsl #1
76 sub ip, ip, r3, lsl #2
77 sub ip, ip, r3, lsl #3
78 mov r3, #0
87 lsr r3, r2, #16
88 cmp r3, r1
89 movhs r2, r3
92 lsr r3, r2, #8
[all …]
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| /external/boringssl/linux-arm/crypto/sha/ |
| D | sha1-armv4-large.S | 12 sub r3,pc,#8 @ sha1_block_data_order
14 ldr r12,[r3,r12] @ OPENSSL_armcap_P
25 ldmia r0,{r3,r4,r5,r6,r7}
43 add r7,r7,r3,ror#27 @ E+=ROR(A,27)
49 add r7,r7,r3,ror#27 @ E+=ROR(A,27)
79 and r10,r3,r10,ror#2
91 eor r10,r3,r4 @ F_xx_xx
98 eor r10,r3,r4 @ F_xx_xx
116 eor r10,r7,r3 @ F_xx_xx
123 eor r10,r7,r3 @ F_xx_xx
[all …]
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| /external/libmpeg2/common/arm/ |
| D | impeg2_inter_pred.s | 110 vst1.8 {d0, d1}, [r5], r3 @Store and increment dst
114 vst1.8 {d0, d1}, [r5], r3 @Store and increment dst
116 vst1.8 {d0, d1}, [r5], r3 @Store and increment dst
118 vst1.8 {d0, d1}, [r5], r3 @Store and increment dst
120 vst1.8 {d0, d1}, [r5], r3 @Store and increment dst
122 vst1.8 {d0, d1}, [r5], r3 @Store and increment dst
124 vst1.8 {d0, d1}, [r5], r3 @Store and increment dst
126 vst1.8 {d0, d1}, [r5], r3 @Store and increment dst
128 vst1.8 {d0, d1}, [r5], r3 @Store and increment dst
130 vst1.8 {d0, d1}, [r5], r3 @Store and increment dst
[all …]
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| D | impeg2_format_conv.s | 144 vst1.8 {q0}, [r3]!
157 sub r3, r3, r6
160 vst1.8 {q0}, [r3]!
164 add r3, r3, r8
170 ldr r3, [sp, #24] @// Load pu1_dest_uv from stack
187 ldr r3, [sp, #24] @// Load pu1_dest_uv from stack
197 vst2.8 {d0, d1}, [r3]!
211 sub r3, r3, r6, lsl #1
215 vst2.8 {d0, d1}, [r3]!
220 add r3, r3, r8
[all …]
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| /external/valgrind/none/tests/s390x/ |
| D | opcodes.h | 22 #define RIE_RRI0(op1,r1,r3,i2,u0,op2) \ argument
23 ".short 0x" #op1 #r1 #r3 "\n\t" \
25 #define RRF_R0RR2(op,r3,u0,r1,r2) ".long 0x" #op #r3 #u0 #r1 #r2 "\n\t" argument
68 #define RSY_RURD(op1,r1,r3,b2,dl2,dh2,op2) \ argument
69 ".short 0x" #op1 #r1 #r3 "\n\t" \
71 #define RRF_F0FF2(op,r3,u0,r1,r2) ".long 0x" #op #r3 #u0 #r1 #r2 "\n\t" argument
72 #define RRF_FUFF2(op,r3,m4,r1,r2) ".long 0x" #op #r3 #m4 #r1 #r2 "\n\t" argument
76 #define RSY_RRRD(op1,r1,r3,b2,dl2,dh2,op2) \ argument
77 ".short 0x" #op1 #r1 #r3 "\n\t" \
79 #define RSY_AARD(op1,r1,r3,b2,dl2,dh2,op2) \ argument
[all …]
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| /external/tremolo/Tremolo/ |
| D | bitwiseARM.s | 46 LDMIA r0,{r2,r3,r12}
48 @ r3 = ptr
53 LDR r10,[r3] @ r10= ptr[0]
56 LDRLT r11,[r3,#4]! @ r11= ptr[1]
78 LDR r10,[r3],#4 @ r10= ptr[0]
79 LDRLT r6,[r3] @ r6 = ptr[1]
162 LDMIA r0,{r2,r3,r12}
164 @ r3 = ptr
170 ADDLE r3,r3,#4
171 STMIA r0,{r2,r3,r12}
[all …]
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| /external/llvm/test/MC/Disassembler/ARM/ |
| D | thumb1.txt | 25 # CHECK: adds r1, r2, r3
48 # CHECK: add sp, r3
59 # CHECK: adr r3, #1020
67 # CHECK: asrs r2, r3, #32
68 # CHECK: asrs r2, r3, #5
69 # CHECK: asrs r2, r3, #1
132 # CHECK: cmp r3, r4
149 # CHECK: ldm r3, {r0, r1, r2, r3, r4, r5, r6, r7}
150 # CHECK: ldm r2!, {r1, r3, r4, r5, r7}
163 # CHECK: ldr r3, [r7, #124]
[all …]
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