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Searched refs:r600_pipe_state_add_reg_bo (Results 1 – 4 of 4) sorted by relevance

/external/mesa3d/src/gallium/drivers/r600/
Devergreen_state.c1734 r600_pipe_state_add_reg_bo(rstate, R_028C60_CB_COLOR0_BASE + i * 0x3C, in evergreen_set_framebuffer_state()
1738 r600_pipe_state_add_reg_bo(rstate, R_028C70_CB_COLOR0_INFO + i * 0x3C, in evergreen_set_framebuffer_state()
1746 r600_pipe_state_add_reg_bo(rstate, R_028C74_CB_COLOR0_ATTRIB + i * 0x3C, in evergreen_set_framebuffer_state()
1748 r600_pipe_state_add_reg_bo(rstate, R_028C7C_CB_COLOR0_CMASK + i * 0x3c, in evergreen_set_framebuffer_state()
1752 r600_pipe_state_add_reg_bo(rstate, R_028C84_CB_COLOR0_FMASK + i * 0x3c, in evergreen_set_framebuffer_state()
1765 r600_pipe_state_add_reg_bo(rstate, R_028C70_CB_COLOR0_INFO + 1 * 0x3C, in evergreen_set_framebuffer_state()
1798 r600_pipe_state_add_reg_bo(rstate, R_028048_DB_Z_READ_BASE, surf->db_depth_base, in evergreen_set_framebuffer_state()
1800 r600_pipe_state_add_reg_bo(rstate, R_028050_DB_Z_WRITE_BASE, surf->db_depth_base, in evergreen_set_framebuffer_state()
1804 r600_pipe_state_add_reg_bo(rstate, R_02804C_DB_STENCIL_READ_BASE, surf->db_stencil_base, in evergreen_set_framebuffer_state()
1806 r600_pipe_state_add_reg_bo(rstate, R_028054_DB_STENCIL_WRITE_BASE, surf->db_stencil_base, in evergreen_set_framebuffer_state()
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Devergreen_compute_internal.c303 r600_pipe_state_add_reg_bo(state, R_028C60_CB_COLOR0_BASE + id * 0x3C, in evergreen_set_rat()
307 r600_pipe_state_add_reg_bo(state, R_028C70_CB_COLOR0_INFO + id * 0x3C, in evergreen_set_rat()
315 r600_pipe_state_add_reg_bo(state, R_028C74_CB_COLOR0_ATTRIB + id * 0x3C, in evergreen_set_rat()
Dr600_state.c1632 r600_pipe_state_add_reg_bo(rstate, R_028040_CB_COLOR0_BASE + i * 4, in r600_set_framebuffer_state()
1634 r600_pipe_state_add_reg_bo(rstate, R_0280A0_CB_COLOR0_INFO + i * 4, in r600_set_framebuffer_state()
1640 r600_pipe_state_add_reg_bo(rstate, R_0280E0_CB_COLOR0_FRAG + i * 4, in r600_set_framebuffer_state()
1643 r600_pipe_state_add_reg_bo(rstate, R_0280C0_CB_COLOR0_TILE + i * 4, in r600_set_framebuffer_state()
1655 r600_pipe_state_add_reg_bo(rstate, R_0280A0_CB_COLOR0_INFO + 1 * 4, in r600_set_framebuffer_state()
1684 r600_pipe_state_add_reg_bo(rstate, R_02800C_DB_DEPTH_BASE, surf->db_depth_base, in r600_set_framebuffer_state()
1688 r600_pipe_state_add_reg_bo(rstate, R_028010_DB_DEPTH_INFO, surf->db_depth_info, in r600_set_framebuffer_state()
2560 r600_pipe_state_add_reg_bo(rstate, in r600_pipe_shader_ps()
2619 r600_pipe_state_add_reg_bo(rstate, in r600_pipe_shader_vs()
2639 r600_pipe_state_add_reg_bo(rstate, R_028894_SQ_PGM_START_FS, in r600_fetch_shader()
Dr600.h228 #define r600_pipe_state_add_reg_bo(state, offset, value, bo, usage) _r600_pipe_state_add_reg_bo(rct… macro