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Searched refs:raddhn2 (Results 1 – 16 of 16) sorted by relevance

/external/llvm/test/MC/AArch64/
Dneon-3vdiff.s393 raddhn2 v0.16b, v1.8h, v2.8h
394 raddhn2 v0.8h, v1.4s, v2.4s
395 raddhn2 v0.4s, v1.2d, v2.2d
Dneon-diagnostics.s2805 raddhn2 v0.16b, v1.8h, v2.8b
2806 raddhn2 v0.8h, v1.4s, v2.4h
2807 raddhn2 v0.4s, v1.2d, v2.2s
/external/libmpeg2/common/armv8/
Dimpeg2_idct.s243 raddhn2 v12.8h, v0.4s, v10.4s
253 raddhn2 v12.8h, v0.4s, v10.4s
263 raddhn2 v12.8h, v0.4s, v10.4s
273 raddhn2 v12.8h, v0.4s, v10.4s
283 raddhn2 v12.8h, v0.4s, v10.4s
293 raddhn2 v12.8h, v0.4s, v10.4s
303 raddhn2 v12.8h, v0.4s, v10.4s
313 raddhn2 v12.8h, v0.4s, v10.4s
/external/llvm/test/CodeGen/AArch64/
Darm64-vecFold.ll84 ; CHECK-NEXT: raddhn2.8h v0, v2, v3
Darm64-vadd.ll95 ;CHECK-NEXT: raddhn2.16b
105 ;CHECK-NEXT: raddhn2.8h
115 ;CHECK-NEXT: raddhn2.4s
Darm64-neon-3vdiff.ll739 ; CHECK: raddhn2 {{v[0-9]+}}.16b, {{v[0-9]+}}.8h, {{v[0-9]+}}.8h
751 ; CHECK: raddhn2 {{v[0-9]+}}.8h, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s
763 ; CHECK: raddhn2 {{v[0-9]+}}.4s, {{v[0-9]+}}.2d, {{v[0-9]+}}.2d
775 ; CHECK: raddhn2 {{v[0-9]+}}.16b, {{v[0-9]+}}.8h, {{v[0-9]+}}.8h
787 ; CHECK: raddhn2 {{v[0-9]+}}.8h, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s
799 ; CHECK: raddhn2 {{v[0-9]+}}.4s, {{v[0-9]+}}.2d, {{v[0-9]+}}.2d
/external/llvm/test/MC/Disassembler/AArch64/
Dneon-instructions.txt1451 # CHECK: raddhn2 v0.16b, v1.8h, v2.8h
1452 # CHECK: raddhn2 v0.8h, v1.4s, v2.4s
1453 # CHECK: raddhn2 v0.4s, v1.2d, v2.2d
/external/valgrind/none/tests/arm64/
Dfp_and_simd.c2738 GEN_BINARY_TEST(raddhn2, 4s, 2d, 2d)
2740 GEN_BINARY_TEST(raddhn2, 8h, 4s, 4s)
2742 GEN_BINARY_TEST(raddhn2, 16b, 8h, 8h)
Dfp_and_simd.stdout.exp26960 raddhn2 v9.4s, v7.2d, v8.2d 990fbf7ca3b8bd7e248f7a06ba2aa3ff 400cadbe2c9df48e29f94337c64ff068 d9…
26962 raddhn2 v9.8h, v7.4s, v8.4s b3ac2036abb6494beb317c980a26c684 463423763a5ada1dd6e00984602a2495 f9…
26964 raddhn2 v9.16b, v7.8h, v8.8h a6dfba3fc14cbf548e63f38b1d224047 39a176fb0c7bf087b64529f1b31436de e…
/external/vixl/src/vixl/a64/
Dsimulator-a64.h2266 V(raddhn2) \
Dmacro-assembler-a64.h2123 V(raddhn2, Raddhn2) \
Dassembler-a64.h3491 void raddhn2(const VRegister& vd,
Dsimulator-a64.cc2802 case NEON_RADDHN2: raddhn2(vf, rd, rn, rm); break; in VisitNEON3Different()
Dlogic-a64.cc3336 LogicVRegister Simulator::raddhn2(VectorFormat vform, in raddhn2() function in vixl::Simulator
Dassembler-a64.cc2413 V(raddhn2, NEON_RADDHN2, vd.IsQ()) \
/external/vixl/doc/
Dsupported-instructions.md2827 void raddhn2(const VRegister& vd,