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Searched refs:res10 (Results 1 – 12 of 12) sorted by relevance

/external/llvm/test/Bitcode/
DmiscInstructions.3.2.ll96 ; CHECK-NEXT: %res10 = icmp sle i32 %x1, %x2
97 %res10 = icmp sle i32 %x1, %x2
138 ; CHECK-NEXT: %res10 = fcmp ole float %x1, %x2
139 %res10 = fcmp ole float %x1, %x2
DmemInstructions.3.2.ll57 ; CHECK-NEXT: %res10 = load volatile i8, i8* %ptr1, !invariant.load !1
58 %res10 = load volatile i8, i8* %ptr1, !invariant.load !1
113 ; CHECK-NEXT: %res10 = load atomic i8, i8* %ptr1 singlethread monotonic, align 1
114 %res10 = load atomic i8, i8* %ptr1 singlethread monotonic, align 1
266 ; CHECK-NEXT: %res10 = extractvalue { i32, i1 } [[TMP]], 0
267 %res10 = cmpxchg volatile i32* %ptr, i32 %cmp, i32 %new release monotonic
/external/llvm/test/CodeGen/R600/
Dllvm.SI.resinfo.ll32 %res10 = call <4 x i32> @llvm.SI.resinfo(i32 %a10, <32 x i8> undef, i32 10)
58 %t10 = extractelement <4 x i32> %res10, i32 2
59 %t11 = extractelement <4 x i32> %res10, i32 3
Dllvm.SI.imageload.ll38 %res10 = call <4 x i32> @llvm.SI.imageload.(<4 x i32> %v10,
56 %t10 = extractelement <4 x i32> %res10, i32 2
57 %t11 = extractelement <4 x i32> %res10, i32 3
Dllvm.AMDGPU.tex.ll31 %res10 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %res9, i32 0, i32 0, i32 10)
32 %res11 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %res10, i32 0, i32 0, i32 11)
Dllvm.SI.sampled.ll56 %res10 = call <4 x float> @llvm.SI.sampled.(<4 x i32> %v10,
89 %t10 = extractelement <4 x float> %res10, i32 2
90 %t11 = extractelement <4 x float> %res10, i32 3
Dllvm.SI.sample.ll56 %res10 = call <4 x float> @llvm.SI.sample.(<4 x i32> %v10,
89 %t10 = extractelement <4 x float> %res10, i32 2
90 %t11 = extractelement <4 x float> %res10, i32 3
Dfetch-limits.r700+.ll48 %res10 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %10, i32 0, i32 0, i32 1)
60 %f = fadd <4 x float> %res10, %res11
/external/clang/test/SemaCXX/
Daltivec.cpp29 int res10[vec_step(vi) == 4 ? 1 : -1]; in test_vec_step() local
/external/llvm/test/CodeGen/ARM/
Dintrinsics-crypto.ll41 %res10 = call <4 x i32> @llvm.arm.neon.sha256su0(<4 x i32> %res9, <4 x i32> %tmp3)
43 ret <4 x i32> %res10
/external/clang/test/SemaOpenCL/
Dvec_step.cl25 int res10[vec_step(int8) == 8 ? 1 : -1];
/external/libvpx/libvpx/vp9/encoder/x86/
Dvp9_dct_sse2.c1357 __m128i res08, res09, res10, res11, res12, res13, res14, res15; in vp9_fdct16x16_sse2() local
1583 res10 = _mm_packs_epi32(w4, w5); in vp9_fdct16x16_sse2()
1868 const __m128i tr0_1 = _mm_unpacklo_epi16(res10, res11); in vp9_fdct16x16_sse2()
1870 const __m128i tr0_3 = _mm_unpackhi_epi16(res10, res11); in vp9_fdct16x16_sse2()