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Searched refs:res5 (Results 1 – 22 of 22) sorted by relevance

/external/llvm/test/Bitcode/
DbinaryFloatInstructions.3.2.ll22 ; CHECK-NEXT: %res5 = fadd x86_fp80 %x5, %x5
23 %res5 = fadd x86_fp80 %x5, %x5
45 ; CHECK-NEXT: %res5 = fadd <16 x float> %x5, %x5
46 %res5 = fadd <16 x float> %x5, %x5
65 ; CHECK-NEXT: %res5 = fadd <16 x double> %x5, %x5
66 %res5 = fadd <16 x double> %x5, %x5
85 ; CHECK-NEXT: %res5 = fadd <16 x half> %x5, %x5
86 %res5 = fadd <16 x half> %x5, %x5
DbinaryIntInstructions.3.2.ll22 ; CHECK-NEXT: %res5 = add i64 %x5, %x5
23 %res5 = add i64 %x5, %x5
51 ; CHECK-NEXT: %res5 = add nuw nsw <16 x i8> %x5, %x5
52 %res5 = add nuw nsw <16 x i8> %x5, %x5
71 ; CHECK-NEXT: %res5 = add nuw nsw <16 x i16> %x5, %x5
72 %res5 = add nuw nsw <16 x i16> %x5, %x5
91 ; CHECK-NEXT: %res5 = add nuw nsw <16 x i32> %x5, %x5
92 %res5 = add nuw nsw <16 x i32> %x5, %x5
111 ; CHECK-NEXT: %res5 = add nuw nsw <16 x i64> %x5, %x5
112 %res5 = add nuw nsw <16 x i64> %x5, %x5
DmiscInstructions.3.2.ll81 ; CHECK-NEXT: %res5 = icmp ult i32 %x1, %x2
82 %res5 = icmp ult i32 %x1, %x2
123 ; CHECK-NEXT: %res5 = fcmp ult float %x1, %x2
124 %res5 = fcmp ult float %x1, %x2
DmemInstructions.3.2.ll42 ; CHECK-NEXT: %res5 = load i8, i8* %ptr1, !nontemporal !0
43 %res5 = load i8, i8* %ptr1, !nontemporal !0
98 ; CHECK-NEXT: %res5 = load atomic volatile i8, i8* %ptr1 unordered, align 1
99 %res5 = load atomic volatile i8, i8* %ptr1 unordered, align 1
245 ; CHECK-NEXT: %res5 = extractvalue { i32, i1 } [[TMP]], 0
246 %res5 = cmpxchg i32* %ptr, i32 %cmp, i32 %new acquire acquire
/external/icu/icu4c/source/test/intltest/
Dnmfmapts.cpp122 UnicodeString res1, res2, res3, res4, res5, res6; in testAPI() local
138 res5 = cur_fr->format(fD, res5, pos3, status); in testAPI()
142 logln((UnicodeString) "" + (int32_t) fD.getDouble() + " formatted to " + res5); in testAPI()
330 UnicodeString res0, res1, res2, res3, res4, res5; in testRegistration() local
340 f5->format(n, res5); in testRegistration()
351 logln((UnicodeString)"f5 unreg cur: " + res5); in testRegistration()
369 if (res5 != res2) { in testRegistration()
/external/icu/icu4j/main/tests/core/src/com/ibm/icu/dev/test/format/
DIntlTestNumberFormatAPI.java86 StringBuffer res5 = new StringBuffer(); in TestAPI() local
105 res5 = cur_fr.format(d, res5, pos3); in TestAPI()
106 logln("" + d + " formatted to " + res5); in TestAPI()
/external/llvm/test/CodeGen/X86/
Davx512bw-intrinsics.ll85 %res5 = call i64 @llvm.x86.avx512.mask.cmp.b.512(<64 x i8> %a0, <64 x i8> %a1, i8 5, i64 -1)
86 %vec5 = insertelement <8 x i64> %vec4, i64 %res5, i32 5
114 %res5 = call i64 @llvm.x86.avx512.mask.cmp.b.512(<64 x i8> %a0, <64 x i8> %a1, i8 5, i64 %mask)
115 %vec5 = insertelement <8 x i64> %vec4, i64 %res5, i32 5
145 %res5 = call i64 @llvm.x86.avx512.mask.ucmp.b.512(<64 x i8> %a0, <64 x i8> %a1, i8 5, i64 -1)
146 %vec5 = insertelement <8 x i64> %vec4, i64 %res5, i32 5
174 %res5 = call i64 @llvm.x86.avx512.mask.ucmp.b.512(<64 x i8> %a0, <64 x i8> %a1, i8 5, i64 %mask)
175 %vec5 = insertelement <8 x i64> %vec4, i64 %res5, i32 5
205 %res5 = call i32 @llvm.x86.avx512.mask.cmp.w.512(<32 x i16> %a0, <32 x i16> %a1, i8 5, i32 -1)
206 %vec5 = insertelement <8 x i32> %vec4, i32 %res5, i32 5
[all …]
Davx512vl-intrinsics.ll87 %res5 = call i8 @llvm.x86.avx512.mask.cmp.d.256(<8 x i32> %a0, <8 x i32> %a1, i8 5, i8 -1)
88 %vec5 = insertelement <8 x i8> %vec4, i8 %res5, i32 5
116 %res5 = call i8 @llvm.x86.avx512.mask.cmp.d.256(<8 x i32> %a0, <8 x i32> %a1, i8 5, i8 %mask)
117 %vec5 = insertelement <8 x i8> %vec4, i8 %res5, i32 5
147 %res5 = call i8 @llvm.x86.avx512.mask.ucmp.d.256(<8 x i32> %a0, <8 x i32> %a1, i8 5, i8 -1)
148 %vec5 = insertelement <8 x i8> %vec4, i8 %res5, i32 5
176 %res5 = call i8 @llvm.x86.avx512.mask.ucmp.d.256(<8 x i32> %a0, <8 x i32> %a1, i8 5, i8 %mask)
177 %vec5 = insertelement <8 x i8> %vec4, i8 %res5, i32 5
207 %res5 = call i8 @llvm.x86.avx512.mask.cmp.q.256(<4 x i64> %a0, <4 x i64> %a1, i8 5, i8 -1)
208 %vec5 = insertelement <8 x i8> %vec4, i8 %res5, i32 5
[all …]
Davx512bwvl-intrinsics.ll87 %res5 = call i32 @llvm.x86.avx512.mask.cmp.b.256(<32 x i8> %a0, <32 x i8> %a1, i8 5, i32 -1)
88 %vec5 = insertelement <8 x i32> %vec4, i32 %res5, i32 5
116 %res5 = call i32 @llvm.x86.avx512.mask.cmp.b.256(<32 x i8> %a0, <32 x i8> %a1, i8 5, i32 %mask)
117 %vec5 = insertelement <8 x i32> %vec4, i32 %res5, i32 5
147 %res5 = call i32 @llvm.x86.avx512.mask.ucmp.b.256(<32 x i8> %a0, <32 x i8> %a1, i8 5, i32 -1)
148 %vec5 = insertelement <8 x i32> %vec4, i32 %res5, i32 5
176 %res5 = call i32 @llvm.x86.avx512.mask.ucmp.b.256(<32 x i8> %a0, <32 x i8> %a1, i8 5, i32 %mask)
177 %vec5 = insertelement <8 x i32> %vec4, i32 %res5, i32 5
207 %res5 = call i16 @llvm.x86.avx512.mask.cmp.w.256(<16 x i16> %a0, <16 x i16> %a1, i8 5, i16 -1)
208 %vec5 = insertelement <8 x i16> %vec4, i16 %res5, i32 5
[all …]
Davx512-intrinsics.ll754 %res5 = call i16 @llvm.x86.avx512.mask.cmp.d.512(<16 x i32> %a0, <16 x i32> %a1, i8 5, i16 -1)
755 %vec5 = insertelement <8 x i16> %vec4, i16 %res5, i32 5
783 %res5 = call i16 @llvm.x86.avx512.mask.cmp.d.512(<16 x i32> %a0, <16 x i32> %a1, i8 5, i16 %mask)
784 %vec5 = insertelement <8 x i16> %vec4, i16 %res5, i32 5
814 %res5 = call i16 @llvm.x86.avx512.mask.ucmp.d.512(<16 x i32> %a0, <16 x i32> %a1, i8 5, i16 -1)
815 %vec5 = insertelement <8 x i16> %vec4, i16 %res5, i32 5
843 %res5 = call i16 @llvm.x86.avx512.mask.ucmp.d.512(<16 x i32> %a0, <16 x i32> %a1, i8 5, i16 %mask)
844 %vec5 = insertelement <8 x i16> %vec4, i16 %res5, i32 5
874 %res5 = call i8 @llvm.x86.avx512.mask.cmp.q.512(<8 x i64> %a0, <8 x i64> %a1, i8 5, i8 -1)
875 %vec5 = insertelement <8 x i8> %vec4, i8 %res5, i32 5
[all …]
/external/llvm/test/CodeGen/R600/
Dfetch-limits.r600.ll26 %res5 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %5, i32 0, i32 0, i32 1)
32 %c = fadd <4 x float> %res4, %res5
Dllvm.SI.resinfo.ll27 %res5 = call <4 x i32> @llvm.SI.resinfo(i32 %a5, <32 x i8> undef, i32 5)
43 %t0 = extractelement <4 x i32> %res5, i32 0
44 %t1 = extractelement <4 x i32> %res5, i32 1
Dllvm.SI.imageload.ll34 %res5 = call <4 x i32> @llvm.SI.imageload.(<4 x i32> %v5,
50 %t0 = extractelement <4 x i32> %res5, i32 0
51 %t1 = extractelement <4 x i32> %res5, i32 1
Dllvm.AMDGPU.tex.ll26 %res5 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %res4, i32 0, i32 0, i32 5)
27 %res6 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %res5, i32 0, i32 0, i32 6)
Dllvm.SI.sampled.ll46 %res5 = call <4 x float> @llvm.SI.sampled.(<4 x i32> %v5,
74 %t0 = extractelement <4 x float> %res5, i32 0
75 %t1 = extractelement <4 x float> %res5, i32 1
Dllvm.SI.sample.ll46 %res5 = call <4 x float> @llvm.SI.sample.(<4 x i32> %v5,
74 %t0 = extractelement <4 x float> %res5, i32 0
75 %t1 = extractelement <4 x float> %res5, i32 1
Dfetch-limits.r700+.ll43 %res5 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %5, i32 0, i32 0, i32 1)
57 %c = fadd <4 x float> %res4, %res5
/external/clang/test/SemaCXX/
Daltivec.cpp24 int res5[vec_step(vbs) == 8 ? 1 : -1]; in test_vec_step() local
/external/llvm/test/CodeGen/ARM/
Dintrinsics-crypto.ll31 %res5 = call <4 x i32> @llvm.arm.neon.sha1su0(<4 x i32> %res4, <4 x i32> %tmp3, <4 x i32> %res1)
33 %res6 = call <4 x i32> @llvm.arm.neon.sha1su1(<4 x i32> %res5, <4 x i32> %res1)
/external/clang/test/SemaOpenCL/
Dvec_step.cl20 int res5[vec_step(auto3) == 1 ? 1 : -1];
/external/clang/test/SemaObjCXX/
Darc-templates.mm134 identity<__weak id> res5 = accept_any_ref(wi);
154 identity<__weak A *> res5 = accept_any_ref(wi);
/external/libvpx/libvpx/vp9/encoder/x86/
Dvp9_dct_sse2.c489 __m128i res0, res1, res2, res3, res4, res5, res6, res7; in vp9_fdct8x8_sse2() local
601 res5 = _mm_packs_epi32(w4, w5); in vp9_fdct8x8_sse2()
618 const __m128i tr0_4 = _mm_unpacklo_epi16(res4, res5); in vp9_fdct8x8_sse2()
620 const __m128i tr0_6 = _mm_unpackhi_epi16(res4, res5); in vp9_fdct8x8_sse2()