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Searched refs:res6 (Results 1 – 22 of 22) sorted by relevance

/external/icu/icu4j/main/tests/core/src/com/ibm/icu/dev/test/format/
DIntlTestNumberFormatAPI.java87 StringBuffer res6 = new StringBuffer(); in TestAPI() local
108 res6 = cur_fr.format(l, res6, pos4); in TestAPI()
109 logln("" + l + " formatted to " + res6); in TestAPI()
/external/llvm/test/CodeGen/X86/
Davx512bw-intrinsics.ll88 %res6 = call i64 @llvm.x86.avx512.mask.cmp.b.512(<64 x i8> %a0, <64 x i8> %a1, i8 6, i64 -1)
89 %vec6 = insertelement <8 x i64> %vec5, i64 %res6, i32 6
117 %res6 = call i64 @llvm.x86.avx512.mask.cmp.b.512(<64 x i8> %a0, <64 x i8> %a1, i8 6, i64 %mask)
118 %vec6 = insertelement <8 x i64> %vec5, i64 %res6, i32 6
148 %res6 = call i64 @llvm.x86.avx512.mask.ucmp.b.512(<64 x i8> %a0, <64 x i8> %a1, i8 6, i64 -1)
149 %vec6 = insertelement <8 x i64> %vec5, i64 %res6, i32 6
177 %res6 = call i64 @llvm.x86.avx512.mask.ucmp.b.512(<64 x i8> %a0, <64 x i8> %a1, i8 6, i64 %mask)
178 %vec6 = insertelement <8 x i64> %vec5, i64 %res6, i32 6
208 %res6 = call i32 @llvm.x86.avx512.mask.cmp.w.512(<32 x i16> %a0, <32 x i16> %a1, i8 6, i32 -1)
209 %vec6 = insertelement <8 x i32> %vec5, i32 %res6, i32 6
[all …]
Davx512vl-intrinsics.ll90 %res6 = call i8 @llvm.x86.avx512.mask.cmp.d.256(<8 x i32> %a0, <8 x i32> %a1, i8 6, i8 -1)
91 %vec6 = insertelement <8 x i8> %vec5, i8 %res6, i32 6
119 %res6 = call i8 @llvm.x86.avx512.mask.cmp.d.256(<8 x i32> %a0, <8 x i32> %a1, i8 6, i8 %mask)
120 %vec6 = insertelement <8 x i8> %vec5, i8 %res6, i32 6
150 %res6 = call i8 @llvm.x86.avx512.mask.ucmp.d.256(<8 x i32> %a0, <8 x i32> %a1, i8 6, i8 -1)
151 %vec6 = insertelement <8 x i8> %vec5, i8 %res6, i32 6
179 %res6 = call i8 @llvm.x86.avx512.mask.ucmp.d.256(<8 x i32> %a0, <8 x i32> %a1, i8 6, i8 %mask)
180 %vec6 = insertelement <8 x i8> %vec5, i8 %res6, i32 6
210 %res6 = call i8 @llvm.x86.avx512.mask.cmp.q.256(<4 x i64> %a0, <4 x i64> %a1, i8 6, i8 -1)
211 %vec6 = insertelement <8 x i8> %vec5, i8 %res6, i32 6
[all …]
Davx512bwvl-intrinsics.ll90 %res6 = call i32 @llvm.x86.avx512.mask.cmp.b.256(<32 x i8> %a0, <32 x i8> %a1, i8 6, i32 -1)
91 %vec6 = insertelement <8 x i32> %vec5, i32 %res6, i32 6
119 %res6 = call i32 @llvm.x86.avx512.mask.cmp.b.256(<32 x i8> %a0, <32 x i8> %a1, i8 6, i32 %mask)
120 %vec6 = insertelement <8 x i32> %vec5, i32 %res6, i32 6
150 %res6 = call i32 @llvm.x86.avx512.mask.ucmp.b.256(<32 x i8> %a0, <32 x i8> %a1, i8 6, i32 -1)
151 %vec6 = insertelement <8 x i32> %vec5, i32 %res6, i32 6
179 %res6 = call i32 @llvm.x86.avx512.mask.ucmp.b.256(<32 x i8> %a0, <32 x i8> %a1, i8 6, i32 %mask)
180 %vec6 = insertelement <8 x i32> %vec5, i32 %res6, i32 6
210 %res6 = call i16 @llvm.x86.avx512.mask.cmp.w.256(<16 x i16> %a0, <16 x i16> %a1, i8 6, i16 -1)
211 %vec6 = insertelement <8 x i16> %vec5, i16 %res6, i32 6
[all …]
Davx512-intrinsics.ll757 %res6 = call i16 @llvm.x86.avx512.mask.cmp.d.512(<16 x i32> %a0, <16 x i32> %a1, i8 6, i16 -1)
758 %vec6 = insertelement <8 x i16> %vec5, i16 %res6, i32 6
786 %res6 = call i16 @llvm.x86.avx512.mask.cmp.d.512(<16 x i32> %a0, <16 x i32> %a1, i8 6, i16 %mask)
787 %vec6 = insertelement <8 x i16> %vec5, i16 %res6, i32 6
817 %res6 = call i16 @llvm.x86.avx512.mask.ucmp.d.512(<16 x i32> %a0, <16 x i32> %a1, i8 6, i16 -1)
818 %vec6 = insertelement <8 x i16> %vec5, i16 %res6, i32 6
846 %res6 = call i16 @llvm.x86.avx512.mask.ucmp.d.512(<16 x i32> %a0, <16 x i32> %a1, i8 6, i16 %mask)
847 %vec6 = insertelement <8 x i16> %vec5, i16 %res6, i32 6
877 %res6 = call i8 @llvm.x86.avx512.mask.cmp.q.512(<8 x i64> %a0, <8 x i64> %a1, i8 6, i8 -1)
878 %vec6 = insertelement <8 x i8> %vec5, i8 %res6, i32 6
[all …]
/external/icu/icu4c/source/test/intltest/
Dnmfmapts.cpp122 UnicodeString res1, res2, res3, res4, res5, res6; in testAPI() local
145 res6 = cur_fr->format(fL, res6, pos4, status); in testAPI()
149 logln((UnicodeString) "" + fL.getLong() + " formatted to " + res6); in testAPI()
/external/llvm/test/Bitcode/
DmiscInstructions.3.2.ll84 ; CHECK-NEXT: %res6 = icmp ule i32 %x1, %x2
85 %res6 = icmp ule i32 %x1, %x2
126 ; CHECK-NEXT: %res6 = fcmp ule float %x1, %x2
127 %res6 = fcmp ule float %x1, %x2
DmemInstructions.3.2.ll45 ; CHECK-NEXT: %res6 = load volatile i8, i8* %ptr1, !nontemporal !0
46 %res6 = load volatile i8, i8* %ptr1, !nontemporal !0
101 ; CHECK-NEXT: %res6 = load atomic volatile i8, i8* %ptr1 monotonic, align 1
102 %res6 = load atomic volatile i8, i8* %ptr1 monotonic, align 1
249 ; CHECK-NEXT: %res6 = extractvalue { i32, i1 } [[TMP]], 0
250 %res6 = cmpxchg volatile i32* %ptr, i32 %cmp, i32 %new acquire acquire
DbinaryFloatInstructions.3.2.ll25 ; CHECK-NEXT: %res6 = fadd ppc_fp128 %x6, %x6
26 %res6 = fadd ppc_fp128 %x6, %x6
DbinaryIntInstructions.3.2.ll25 ; CHECK: %res6 = add nuw i1 %x1, %x1
26 %res6 = add nuw i1 %x1, %x1
/external/llvm/test/CodeGen/R600/
Dfetch-limits.r600.ll27 %res6 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %6, i32 0, i32 0, i32 1)
33 %d = fadd <4 x float> %res6, %res7
Dllvm.SI.resinfo.ll28 %res6 = call <4 x i32> @llvm.SI.resinfo(i32 %a6, <32 x i8> undef, i32 6)
46 %t2 = extractelement <4 x i32> %res6, i32 0
47 %t3 = extractelement <4 x i32> %res6, i32 2
Dllvm.SI.imageload.ll36 %res6 = call <4 x i32> @llvm.SI.imageload.(<4 x i32> %v6,
53 %t2 = extractelement <4 x i32> %res6, i32 0
54 %t3 = extractelement <4 x i32> %res6, i32 2
Dllvm.AMDGPU.tex.ll27 %res6 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %res5, i32 0, i32 0, i32 6)
28 %res7 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %res6, i32 0, i32 0, i32 7)
Dllvm.SI.sampled.ll48 %res6 = call <4 x float> @llvm.SI.sampled.(<4 x i32> %v6,
77 %t2 = extractelement <4 x float> %res6, i32 0
78 %t3 = extractelement <4 x float> %res6, i32 2
Dllvm.SI.sample.ll48 %res6 = call <4 x float> @llvm.SI.sample.(<4 x i32> %v6,
77 %t2 = extractelement <4 x float> %res6, i32 0
78 %t3 = extractelement <4 x float> %res6, i32 2
Dfetch-limits.r700+.ll44 %res6 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %6, i32 0, i32 0, i32 1)
58 %d = fadd <4 x float> %res6, %res7
/external/clang/test/SemaCXX/
Daltivec.cpp25 int res6[vec_step(vs) == 8 ? 1 : -1]; in test_vec_step() local
/external/llvm/test/CodeGen/ARM/
Dintrinsics-crypto.ll33 %res6 = call <4 x i32> @llvm.arm.neon.sha1su1(<4 x i32> %res5, <4 x i32> %res1)
35 %res7 = call <4 x i32> @llvm.arm.neon.sha256h(<4 x i32> %res6, <4 x i32> %tmp3, <4 x i32> %res1)
/external/clang/test/SemaOpenCL/
Dvec_step.cl21 int res6[vec_step(auto4) == 2 ? 1 : -1];
/external/clang/test/SemaObjCXX/
Darc-templates.mm135 identity<__autoreleasing id> res6 = accept_any_ref(ai);
155 identity<__autoreleasing A *> res6 = accept_any_ref(ai);
/external/libvpx/libvpx/vp9/encoder/x86/
Dvp9_dct_sse2.c489 __m128i res0, res1, res2, res3, res4, res5, res6, res7; in vp9_fdct8x8_sse2() local
540 res6 = _mm_packs_epi32(w6, w7); in vp9_fdct8x8_sse2()
619 const __m128i tr0_5 = _mm_unpacklo_epi16(res6, res7); in vp9_fdct8x8_sse2()
621 const __m128i tr0_7 = _mm_unpackhi_epi16(res6, res7); in vp9_fdct8x8_sse2()