Searched refs:res8 (Results 1 – 16 of 16) sorted by relevance
| /external/mesa3d/src/gallium/drivers/nvc0/ |
| D | nvc0_query.c | 342 boolean *res8 = (boolean*)result; in nvc0_query_result() local
365 res8[0] = TRUE; in nvc0_query_result()
371 res8[0] = q->data[1] != q->data[5]; in nvc0_query_result()
382 res8[0] = data64[0] != data64[2]; in nvc0_query_result()
389 res8[8] = (data64[1] == data64[3]) ? FALSE : TRUE; in nvc0_query_result()
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| /external/llvm/test/Bitcode/ |
| D | miscInstructions.3.2.ll | 90 ; CHECK-NEXT: %res8 = icmp sge i32 %x1, %x2
91 %res8 = icmp sge i32 %x1, %x2
132 ; CHECK-NEXT: %res8 = fcmp oge float %x1, %x2
133 %res8 = fcmp oge float %x1, %x2
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| D | memInstructions.3.2.ll | 51 ; CHECK-NEXT: %res8 = load volatile i8, i8* %ptr1, align 1, !nontemporal !0
52 %res8 = load volatile i8, i8* %ptr1, align 1, !nontemporal !0
107 ; CHECK-NEXT: %res8 = load atomic volatile i8, i8* %ptr1 seq_cst, align 1
108 %res8 = load atomic volatile i8, i8* %ptr1 seq_cst, align 1
257 ; CHECK-NEXT: %res8 = extractvalue { i32, i1 } [[TMP]], 0
258 %res8 = cmpxchg volatile i32* %ptr, i32 %cmp, i32 %new singlethread acquire acquire
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| D | binaryIntInstructions.3.2.ll | 31 ; CHECK: %res8 = add nuw nsw i1 %x1, %x1
32 %res8 = add nuw nsw i1 %x1, %x1
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| /external/mesa3d/src/gallium/drivers/nv50/ |
| D | nv50_query.c | 253 boolean *res8 = (boolean *)result; in nv50_query_result() local
274 res8[0] = TRUE; in nv50_query_result()
292 res8[8] = (data64[1] == data64[3]) ? FALSE : TRUE; in nv50_query_result()
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| /external/llvm/test/CodeGen/R600/ |
| D | fetch-limits.r600.ll | 29 %res8 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %8, i32 0, i32 0, i32 1)
34 %e = fadd <4 x float> %res8, %a
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| D | llvm.SI.resinfo.ll | 30 %res8 = call <4 x i32> @llvm.SI.resinfo(i32 %a8, <32 x i8> undef, i32 8)
52 %t6 = extractelement <4 x i32> %res8, i32 1
53 %t7 = extractelement <4 x i32> %res8, i32 2
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| D | llvm.AMDGPU.tex.ll | 29 %res8 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %res7, i32 0, i32 0, i32 8)
30 %res9 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %res8, i32 0, i32 0, i32 9)
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| D | llvm.SI.sampled.ll | 52 %res8 = call <4 x float> @llvm.SI.sampled.(<4 x i32> %v8,
83 %t6 = extractelement <4 x float> %res8, i32 1
84 %t7 = extractelement <4 x float> %res8, i32 2
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| D | llvm.SI.sample.ll | 52 %res8 = call <4 x float> @llvm.SI.sample.(<4 x i32> %v8,
83 %t6 = extractelement <4 x float> %res8, i32 1
84 %t7 = extractelement <4 x float> %res8, i32 2
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| D | fetch-limits.r700+.ll | 46 %res8 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %8, i32 0, i32 0, i32 1)
59 %e = fadd <4 x float> %res8, %res9
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| /external/clang/test/SemaCXX/ |
| D | altivec.cpp | 27 int res8[vec_step(vp) == 8 ? 1 : -1]; in test_vec_step() local
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| /external/llvm/test/CodeGen/ARM/ |
| D | intrinsics-crypto.ll | 37 %res8 = call <4 x i32> @llvm.arm.neon.sha256h2(<4 x i32> %res7, <4 x i32> %tmp3, <4 x i32> %res1)
39 %res9 = call <4 x i32> @llvm.arm.neon.sha256su1(<4 x i32> %res8, <4 x i32> %tmp3, <4 x i32> %res1)
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| /external/clang/test/SemaOpenCL/ |
| D | vec_step.cl | 23 int res8[vec_step(int3) == 4 ? 1 : -1];
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| /external/hyphenation-patterns/nb/ |
| D | hyph-nb.pat.txt | 7381 fjæ4res8
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| /external/hyphenation-patterns/nn/ |
| D | hyph-nn.pat.txt | 7381 fjæ4res8
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