| /external/llvm/test/CodeGen/AArch64/ |
| D | arm64-rev.ll | 56 ; CHECK: rev32 x0, x0
130 ;CHECK: rev32.8b
138 ;CHECK: rev32.4h
146 ;CHECK: rev32.16b
154 ;CHECK: rev32.8h
188 ;CHECK: rev32.8h
228 ; CHECK: rev32.16b
|
| D | arm64-big-endian-bitconverts.ll | 286 ; CHECK: rev32 v{{[0-9]+}}.4h
299 ; CHECK: rev32 v{{[0-9]+}}.8b
363 ; CHECK: rev32 v{{[0-9]+}}.4h
376 ; CHECK: rev32 v{{[0-9]+}}.8b
428 ; CHECK: rev32 v{{[0-9]+}}.4h
441 ; CHECK: rev32 v{{[0-9]+}}.4h
506 ; CHECK: rev32 v{{[0-9]+}}.8b
519 ; CHECK: rev32 v{{[0-9]+}}.8b
839 ; CHECK: rev32 v{{[0-9]+}}.8h
853 ; CHECK: rev32 v{{[0-9]+}}.16b
[all …]
|
| D | arm64-vext_reverse.ll | 105 ; CHECK: rev32 v0.4h, v1.4h
137 ; CHECK: rev32 v0.4h, v0.4h
|
| D | fp16-vector-shuffle.ll | 113 ; CHECK: rev32
135 ; CHECK: rev32
|
| D | dp1.ll | 32 ; CHECK: rev32 {{x[0-9]+}}, {{x[0-9]+}}
|
| D | neon-perm.ll | 2376 ; CHECK: rev32 {{v[0-9]+}}.4h, {{v[0-9]+}}.4h
2384 ; CHECK: rev32 {{v[0-9]+}}.8h, {{v[0-9]+}}.8h
2416 ; CHECK: rev32 {{v[0-9]+}}.4h, {{v[0-9]+}}.4h
2424 ; CHECK: rev32 {{v[0-9]+}}.8h, {{v[0-9]+}}.8h
2464 ; CHECK: rev32 {{v[0-9]+}}.4h, {{v[0-9]+}}.4h
2472 ; CHECK: rev32 {{v[0-9]+}}.8h, {{v[0-9]+}}.8h
|
| /external/llvm/test/MC/AArch64/ |
| D | neon-simd-misc.s | 23 rev32 v30.16b, v31.16b
24 rev32 v4.8h, v7.8h
25 rev32 v21.8b, v1.8b
26 rev32 v0.4h, v9.4h
|
| D | neon-diagnostics.s | 5243 rev32 v30.2s, v31.2s
5244 rev32 v30.4s, v31.4s
5245 rev32 v30.2d, v31.2d
|
| D | arm64-arithmetic-encoding.s | 442 rev32 x1, x2
|
| D | basic-a64-instructions.s | 1452 rev32 x20, x1
1453 rev32 x20, xzr
|
| D | arm64-advsimd.s | 490 rev32.8b v0, v0
540 ; CHECK: rev32.8b v0, v0 ; encoding: [0x00,0x08,0x20,0x2e]
|
| /external/boringssl/linux-aarch64/crypto/sha/ |
| D | sha1-armv8.S | 37 rev32 x3,x3
55 rev32 x5,x5
80 rev32 x7,x7
105 rev32 x9,x9
130 rev32 x11,x11
155 rev32 x13,x13
180 rev32 x15,x15
205 rev32 x17,x17
1089 rev32 v4.16b,v4.16b
1090 rev32 v5.16b,v5.16b
[all …]
|
| D | sha256-armv8.S | 1019 rev32 v4.16b,v4.16b
1020 rev32 v5.16b,v5.16b
1021 rev32 v6.16b,v6.16b
1022 rev32 v7.16b,v7.16b
|
| /external/llvm/test/MC/Disassembler/AArch64/ |
| D | arm64-arithmetic.txt | 412 # CHECK: rev32 x1, x2
|
| /external/valgrind/none/tests/arm64/ |
| D | fp_and_simd.c | 3123 GEN_UNARY_TEST(rev32, 16b, 16b)
3124 GEN_UNARY_TEST(rev32, 8b, 8b)
3125 GEN_UNARY_TEST(rev32, 8h, 8h)
3126 GEN_UNARY_TEST(rev32, 4h, 4h)
|
| D | integer.stdout.exp | 1824 rev32 x11,x23 :: rd aeba79fd88b450e5 rn fd79baaee550b488, cin 0, nzcv 00000000
1825 rev32 x11,x23 :: rd 095461e873174245 rn e861540945421773, cin 0, nzcv 00000000
1826 rev32 x11,x23 :: rd d040119a6cbf1dfd rn 9a1140d0fd1dbf6c, cin 0, nzcv 00000000
|
| /external/v8/src/arm64/ |
| D | macro-assembler-arm64-inl.h | 1026 rev32(rd, rn); in Rev32()
|
| D | assembler-arm64.h | 1447 void rev32(const Register& rd, const Register& rn);
|
| D | assembler-arm64.cc | 1551 void Assembler::rev32(const Register& rd, in rev32() function in v8::internal::Assembler
|
| /external/vixl/src/vixl/a64/ |
| D | macro-assembler-a64.h | 1678 rev32(rd, rn); in Rev32()
2265 V(rev32, Rev32) \
|
| D | assembler-a64.h | 1646 void rev32(const Register& rd, const Register& rn);
2808 void rev32(const VRegister& vd,
|
| D | simulator-a64.h | 1777 LogicVRegister rev32(VectorFormat vform,
|
| D | assembler-a64.cc | 1390 void Assembler::rev32(const Register& rd, in rev32() function in vixl::Assembler
3913 void Assembler::rev32(const VRegister& vd, in rev32() function in vixl::Assembler
|
| /external/vixl/doc/ |
| D | supported-instructions.md | 972 void rev32(const Register& rd, const Register& rn)
2852 void rev32(const VRegister& vd,
|
| /external/v8/test/cctest/ |
| D | test-disasm-arm64.cc | 503 COMPARE(rev32(x8, x9), "rev32 x8, x9"); in TEST_()
|