| /external/llvm/test/MC/ARM/ |
| D | arm-shift-encoding.s | 10 ldr r0, [r0, r0, rrx]
20 @ CHECK: ldr r0, [r0, r0, rrx] @ encoding: [0x60,0x00,0x90,0xe7]
30 pld [r0, r0, rrx]
40 @ CHECK: [r0, r0, rrx] @ encoding: [0x60,0xf0,0xd0,0xf7]
50 str r0, [r0, r0, rrx]
60 @ CHECK: str r0, [r0, r0, rrx] @ encoding: [0x60,0x00,0x80,0xe7]
68 ldr r0, [r1], r2, rrx
73 @ CHECK: ldr r0, [r1], r2, rrx @ encoding: [0x62,0x00,0x91,0xe6]
88 adc r7, r2, r12, rrx
98 @ CHECK: adc r7, r2, r12, rrx @ encoding: [0x6c,0x70,0xa2,0xe0]
[all …]
|
| D | thumb-shift-encoding.s | 14 sbc.w r7, r2, r12, rrx
24 @ CHECK: sbc.w r7, r2, r12, rrx @ encoding: [0x62,0xeb,0x3c,0x07]
34 and.w r7, r2, r12, rrx
44 @ CHECK: and.w r7, r2, r12, rrx @ encoding: [0x02,0xea,0x3c,0x07]
|
| D | basic-arm-instructions.s | 86 adc r4, r5, r6, rrx
100 adc r4, r5, rrx
105 adc r4, r5, rrx
124 @ CHECK: adc r4, r5, r6, rrx @ encoding: [0x66,0x40,0xa5,0xe0]
137 @ CHECK: adc r4, r4, r5, rrx @ encoding: [0x65,0x40,0xa4,0xe0]
142 @ CHECK: adc r4, r4, r5, rrx @ encoding: [0x65,0x40,0xa4,0xe0]
205 add r4, r5, r6, rrx
229 add r4, r5, rrx
261 @ CHECK: add r4, r5, r6, rrx @ encoding: [0x66,0x40,0x85,0xe0]
284 @ CHECK: add r4, r4, r5, rrx @ encoding: [0x65,0x40,0x84,0xe0]
[all …]
|
| D | basic-thumb2-instructions.s | 1409 mov r4, r4, rrx
1427 @ CHECK: rrx r4, r4 @ encoding: [0x4f,0xea,0x34,0x04]
1569 mvn r5, r6, rrx
1579 @ CHECK: mvn.w r5, r6, rrx @ encoding: [0x6f,0xea,0x36,0x05]
1946 rrx r1, r2
1952 @ CHECK: rrx r1, r2 @ encoding: [0x4f,0xea,0x32,0x01]
2963 sub.w r5, r2, r12, rrx
2977 @ CHECK: sub.w r5, r2, r12, rrx @ encoding: [0xa2,0xeb,0x3c,0x05]
|
| /external/llvm/test/CodeGen/Thumb2/ |
| D | thumb2-lsr3.ll | 6 ; CHECK: rrx r0, r0
15 ; CHECK: rrx r0, r0
|
| /external/llvm/test/CodeGen/ARM/ |
| D | long_shift.ll | 7 ; CHECK-LE-NEXT: rrx r2, r2
11 ; CHECK-BE-NEXT: rrx r3, r3
|
| /external/llvm/test/MC/Disassembler/ARM/ |
| D | basic-arm-instructions.txt | 60 # CHECK: adc r4, r5, r6, rrx
73 # CHECK: adc r4, r4, r5, rrx
78 # CHECK: adc r4, r4, r5, rrx
133 # CHECK: add r4, r5, r6, rrx
146 # CHECK: add r4, r4, r5, rrx
217 # CHECK: and r10, r1, r6, rrx
230 # CHECK: and r10, r10, r1, rrx
300 # CHECK: bic r10, r1, r6, rrx
313 # CHECK: bic r10, r10, r1, rrx
435 # CHECK: cmn r1, r6, rrx
[all …]
|
| D | arm-tests.txt | 108 # CHECK-NOT: orr r7, r8, r7, rrx #0
109 # CHECK: orr r7, r8, r7, rrx
|
| D | thumb2.txt | 1194 # CHECK: mvn.w r5, r6, rrx
1532 # CHECK: rrx r1, r2
2078 # CHECK: sub.w r5, r2, r12, rrx
|
| /external/llvm/lib/Target/ARM/MCTargetDesc/ |
| D | ARMAddressingModes.h | 33 rrx enumerator
52 case ARM_AM::rrx: return "rrx"; in getShiftOpcStr()
|
| D | ARMMCCodeEmitter.cpp | 212 case ARM_AM::rrx: return 3; in getShiftOp()
1377 case ARM_AM::rrx: in getSORegImmOpValue()
1496 case ARM_AM::rrx: // FALLTHROUGH in getT2SORegOpValue()
1501 if (SOpc == ARM_AM::rrx) in getT2SORegOpValue()
|
| /external/llvm/lib/Target/ARM/InstPrinter/ |
| D | ARMInstPrinter.cpp | 51 if (ShOpc != ARM_AM::rrx) { in printRegImmShift()
151 if (ARM_AM::getSORegShOp(MO2.getImm()) == ARM_AM::rrx) { in printInst()
399 if (ShOpc == ARM_AM::rrx) in printSORegRegOperand()
|
| /external/llvm/lib/Target/ARM/AsmParser/ |
| D | ARMAsmParser.cpp | 3062 .Case("rrx", ARM_AM::rrx) in tryParseShiftRegister()
3082 if (ShiftTy == ARM_AM::rrx) { in tryParseShiftRegister()
3133 if (ShiftReg && ShiftTy != ARM_AM::rrx) in tryParseShiftRegister()
4980 St = ARM_AM::rrx; in parseMemRegOffsetShift()
4987 if (St != ARM_AM::rrx) { in parseMemRegOffsetShift()
7946 case ARM_AM::rrx: isNarrow = false; newOpc = ARM::t2RRX; break; in processInstruction()
8024 unsigned Shifter = ARM_AM::getSORegOpc(ARM_AM::rrx, 0); in processInstruction()
8366 if (SOpc == ARM_AM::rrx || SOpc == ARM_AM::asr || SOpc == ARM_AM::lsr) in processInstruction()
8390 if (SOpc == ARM_AM::rrx) return false; in processInstruction()
|
| /external/llvm/lib/Target/ARM/Disassembler/ |
| D | ARMDisassembler.cpp | 1169 Shift = ARM_AM::rrx; in DecodeSORegImmOperand()
1564 Opc = ARM_AM::rrx; in DecodeAddrMode2IdxInstruction()
1607 ShOp = ARM_AM::rrx; in DecodeSORegMemOperand()
|
| /external/llvm/lib/Target/ARM/ |
| D | ARMExpandPseudoInsts.cpp | 925 .addImm(ARM_AM::getSORegOpc(ARM_AM::rrx, 0))) in ExpandMI()
|
| D | ARMInstrThumb2.td | 44 // Note: We do not support rrx shifted operands yet.
2311 "rrx", "\t$Rd, $Rm",
|
| D | ARMInstrInfo.td | 5632 def RRXi : ARMAsmPseudo<"rrx${s}${p} $Rd, $Rm",
|