Searched refs:s_mov_b64 (Results 1 – 9 of 9) sorted by relevance
| /external/llvm/test/MC/R600/ |
| D | sop1-err.s | 22 s_mov_b64 s1, s[0:1] label
25 s_mov_b64 s[0:1], s1 label
33 s_mov_b64 s[0:1], 0xfffffffff label
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| D | sop1.s | 13 s_mov_b64 s[2:3], s[4:5] label
16 s_mov_b64 s[2:3], 0xffffffffffffffff label
35 s_mov_b64 s[2:3], s[4:5] label
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| /external/llvm/test/CodeGen/R600/ |
| D | valu-i1.ll | 8 ; SI-NOT: s_mov_b64 s[{{[0-9]:[0-9]}}], -1
77 ; SI: s_mov_b64 {{s\[[0-9]+:[0-9]+\]}}, 0{{$}}
121 ; SI: s_mov_b64 [[ZERO:s\[[0-9]+:[0-9]+\]]], 0{{$}}
122 ; SI: s_mov_b64 [[COND_STATE:s\[[0-9]+:[0-9]+\]]], [[ZERO]]
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| D | llvm.amdgpu.kilp.ll | 5 ; SI: s_mov_b64 exec, 0
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| D | llvm.AMDGPU.kill.ll | 6 ; SI: s_mov_b64 exec, 0
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| D | salu-to-valu.ll | 12 ; Make sure we aren't using VGPRs for the source operand of s_mov_b64
13 ; CHECK-NOT: s_mov_b64 s[{{[0-9]+:[0-9]+}}], v
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| D | llvm.AMDGPU.div_fmas.ll | 91 ; SI: s_mov_b64 vcc, 0
100 ; SI: s_mov_b64 vcc, -1
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| D | operand-folding.ll | 40 ; CHECK-NOT: s_mov_b64
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| /external/llvm/lib/Target/R600/ |
| D | SIInstructions.td | 102 defm S_MOV_B64 : SOP1_64 <sop1<0x04, 0x01>, "s_mov_b64", []>;
2894 // We also load this -1 with s_mov_b32 / s_mov_b64 even though this
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