Searched refs:s_or_b64 (Results 1 – 10 of 10) sorted by relevance
| /external/llvm/test/CodeGen/R600/ |
| D | endcf-loop-header.ll | 4 ; loop block. This intrinsic will be lowered to s_or_b64 by the code
10 ; CHECK: s_or_b64 exec, exec
13 ; CHECK-NOT: s_or_b64 exec, exec
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| D | valu-i1.ll | 54 ; SI: s_or_b64 exec, exec, [[BR_SREG]]
83 ; SI: s_or_b64 [[OR_SREG:s\[[0-9]+:[0-9]+\]]]
138 ; SI: s_or_b64 [[COND_STATE]], vcc, [[COND_STATE]]
141 ; SI: s_or_b64 exec, exec, [[ORNEG1]]
142 ; SI: s_or_b64 [[COND_STATE]], [[ORNEG1]], [[COND_STATE]]
147 ; SI: s_or_b64 exec, exec, [[COND_STATE]]
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| D | si-annotate-cf.ll | 8 ; SI: s_or_b64
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| D | or.ll | 87 ; SI: s_or_b64
158 ; SI: s_or_b64 s[{{[0-9]+:[0-9]+}}], vcc, s[{{[0-9]+:[0-9]+}}]
171 ; SI: s_or_b64 s[{{[0-9]+:[0-9]+}}], vcc, s[{{[0-9]+:[0-9]+}}]
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| D | rotl.i64.ll | 8 ; BOTH: s_or_b64
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| D | rotr.i64.ll | 8 ; BOTH: s_or_b64
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| D | llvm.AMDGPU.div_fmas.ll | 149 ; SI: s_or_b64 exec, exec, [[SAVE]]
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| D | llvm.AMDGPU.class.ll | 455 ; SI: s_or_b64
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| /external/llvm/test/MC/R600/ |
| D | sop2.s | 50 s_or_b64 s[2:3], s[4:5], s[6:7] label
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| /external/llvm/lib/Target/R600/ |
| D | SIInstructions.td | 256 defm S_OR_B64 : SOP2_64 <sop2<0x11, 0x0f>, "s_or_b64",
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