| /external/lldb/source/Plugins/Instruction/ARM/ |
| D | EmulateInstructionARM.h | 548 EmulateShiftImm (const uint32_t opcode, const ARMEncoding encoding, ARM_ShifterType shift_type);
552 EmulateShiftReg (const uint32_t opcode, const ARMEncoding encoding, ARM_ShifterType shift_type);
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| D | EmulateInstructionARM.cpp | 3177 …RM::EmulateShiftImm (const uint32_t opcode, const ARMEncoding encoding, ARM_ShifterType shift_type) in EmulateShiftImm() argument
3198 if (shift_type == SRType_ROR && use_encoding == eEncodingT1) in EmulateShiftImm()
3208 if (shift_type == SRType_ROR) in EmulateShiftImm()
3219 if (shift_type == SRType_RRX) in EmulateShiftImm()
3240 if (shift_type == SRType_ROR && imm5 == 0) in EmulateShiftImm()
3241 shift_type = SRType_RRX; in EmulateShiftImm()
3249 uint32_t amt = (shift_type == SRType_RRX ? 1 : DecodeImmShift(shift_type, imm5)); in EmulateShiftImm()
3251 uint32_t result = Shift_C(value, shift_type, amt, APSR_C, carry, &success); in EmulateShiftImm()
3267 …RM::EmulateShiftReg (const uint32_t opcode, const ARMEncoding encoding, ARM_ShifterType shift_type) in EmulateShiftReg() argument
3322 uint32_t result = Shift_C(value, shift_type, amt, APSR_C, carry, &success); in EmulateShiftReg()
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| /external/v8/src/arm64/ |
| D | simulator-arm64.cc | 891 T Simulator::ShiftOperand(T value, Shift shift_type, unsigned amount) { in ShiftOperand() argument
898 switch (shift_type) { in ShiftOperand()
1394 Shift shift_type = static_cast<Shift>(instr->ShiftDP()); in VisitAddSubShifted() local
1398 int64_t op2 = ShiftOperand(xreg(instr->Rm()), shift_type, shift_amount); in VisitAddSubShifted()
1401 int32_t op2 = ShiftOperand(wreg(instr->Rm()), shift_type, shift_amount); in VisitAddSubShifted()
1440 Shift shift_type = static_cast<Shift>(instr->ShiftDP()); in VisitLogicalShifted() local
1444 int64_t op2 = ShiftOperand(xreg(instr->Rm()), shift_type, shift_amount); in VisitLogicalShifted()
1448 int32_t op2 = ShiftOperand(wreg(instr->Rm()), shift_type, shift_amount); in VisitLogicalShifted()
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| D | disasm-arm64.cc | 1540 const char* shift_type[] = {"lsl", "lsr", "asr", "ror"}; in SubstituteShiftField() local
1541 AppendToOutput(", %s #%" PRId64, shift_type[instr->ShiftDP()], in SubstituteShiftField()
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| D | simulator-arm64.h | 696 Shift shift_type,
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| /external/vixl/src/vixl/a64/ |
| D | simulator-a64.cc | 334 Shift shift_type, in ShiftOperand() argument
340 switch (shift_type) { in ShiftOperand()
983 Shift shift_type = static_cast<Shift>(instr->ShiftDP()); in VisitLogicalShifted() local
985 int64_t op2 = ShiftOperand(reg_size, reg(reg_size, instr->Rm()), shift_type, in VisitLogicalShifted()
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| D | simulator-a64.h | 1418 Shift shift_type,
1422 Shift shift_type,
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| D | disasm-a64.cc | 3246 const char* shift_type[] = {"lsl", "lsr", "asr", "ror"}; in SubstituteShiftField() local
3247 AppendToOutput(", %s #%" PRId64, shift_type[instr->ShiftDP()], in SubstituteShiftField()
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| /external/valgrind/VEX/priv/ |
| D | guest_arm_toIR.c | 9066 UInt regD = 99, regN = 99, regM = 99, imm5 = 99, shift_type = 99; in decode_V6MEDIA_instruction() local
9077 shift_type = (INSNT1(5,5) << 1) | 0; in decode_V6MEDIA_instruction()
9090 shift_type = (INSNA(6,6) << 1) | 0; in decode_V6MEDIA_instruction()
9102 dis_buf, &irt_regM_shift, NULL, irt_regM, shift_type, imm5, regM ); in decode_V6MEDIA_instruction()
9126 UInt regD = 99, regN = 99, shift_type = 99, imm5 = 99, sat_imm = 99; in decode_V6MEDIA_instruction() local
9135 shift_type = (INSNT0(5,5) << 1) | 0; in decode_V6MEDIA_instruction()
9140 if (shift_type == BITS2(1,0) && imm5 == 0) in decode_V6MEDIA_instruction()
9148 shift_type = (INSNA(6,6) << 1) | 0; in decode_V6MEDIA_instruction()
9165 irt_regN, shift_type, imm5, regN ); in decode_V6MEDIA_instruction()
9184 UInt regD = 99, regN = 99, shift_type = 99, imm5 = 99, sat_imm = 99; in decode_V6MEDIA_instruction() local
[all …]
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| /external/v8/src/arm/ |
| D | simulator-arm.cc | 2607 int32_t shift_type = instr->Bit(6); in DecodeType3() local
2609 if (shift_type == 0) { // LSL in DecodeType3()
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64InstrFormats.td | 1299 class BaseShift<bits<2> shift_type, RegisterClass regtype, string asm,
1303 let Inst{11-10} = shift_type;
1306 multiclass Shift<bits<2> shift_type, string asm, SDNode OpNode> {
1307 def Wr : BaseShift<shift_type, GPR32, asm> {
1311 def Xr : BaseShift<shift_type, GPR64, asm, OpNode> {
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