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/external/llvm/test/CodeGen/Mips/Fast-ISel/
Dicmpa.ll47 ; CHECK: sltu $[[REG2:[0-9]+]], $zero, $[[REG1]]
48 ; FIXME: This instruction is redundant. The sltu can only produce 0 and 1.
67 ; CHECK: sltu $[[REG1:[0-9]+]], $[[REG_UD]], $[[REG_UC]]
68 ; FIXME: This instruction is redundant. The sltu can only produce 0 and 1.
87 ; CHECK: sltu $[[REG1:[0-9]+]], $[[REG_UC]], $[[REG_UD]]
88 ; FIXME: This instruction is redundant. The sltu can only produce 0 and 1.
106 ; CHECK: sltu $[[REG1:[0-9]+]], $[[REG_UC]], $[[REG_UD]]
108 ; FIXME: This instruction is redundant. The sltu can only produce 0 and 1.
126 ; CHECK: sltu $[[REG1:[0-9]+]], $[[REG_UD]], $[[REG_UC]]
128 ; FIXME: This instruction is redundant. The sltu can only produce 0 and 1.
/external/llvm/test/CodeGen/Mips/
Dllcarry.ll17 ; 16: sltu ${{[0-9]+}}, ${{[0-9]+}}
30 ; 16: sltu ${{[0-9]+}}, ${{[0-9]+}}
43 ; 16: sltu ${{[0-9]+}}, ${{[0-9]+}}
D2008-06-05-Carry.ll6 ; CHECK: sltu
17 ; CHECK: sltu
Dmadd-msub.ll28 ; 32R6-DAG: sltu $[[T2:[0-9]+]], $[[T1]], $6
74 ; 32R6-DAG: sltu $[[T2:[0-9]+]], $[[T1]], $6
112 ; 32R6-DAG: sltu $[[T2:[0-9]+]], $[[T1]], $7
153 ; 32R6-DAG: sltu $[[T3:[0-9]+]], $6, $[[T1]]
200 ; 32R6-DAG: sltu $[[T2:[0-9]+]], $6, $[[T1]]
239 ; 32R6-DAG: sltu $[[T2:[0-9]+]], $7, $[[T1]]
Dsetcc-se.ll16 ; CHECK: sltu ${{[0-9]+}}, $zero, $4
109 ; CHECK: sltu ${{[0-9]+}}
142 ; CHECK: sltu ${{[0-9]+}}
Dcmov.ll396 ; 32-CMOV-DAG: sltu $[[R1:[0-9]+]], $[[I32766]], $5
405 ; 32-CMP-DAG: sltu $[[CC1:[0-9]+]], $[[I32766]], $5
441 ; 32-CMOV-DAG: sltu $[[R1:[0-9]+]], $[[I32766]], $5
450 ; 32-CMP-DAG: sltu $[[CC1:[0-9]+]], $[[I32766]], $5
582 ; 32-CMOV-DAG: sltu $[[R0:[0-9]+]], $[[R1]], $4
588 ; 32-CMP-DAG: sltu $[[R0:[0-9]+]], $[[I32767]], $4
597 ; 64-CMOV-DAG: sltu $[[R0:[0-9]+]], $[[R1]], $4
603 ; 64-CMP-DAG: sltu $[[R0:[0-9]+]], $[[R1]], $4
657 ; 32-CMOV-DAG: sltu $[[R0:[0-9]+]], $[[R1]], $4
664 ; 32-CMP-DAG: sltu $[[R0:[0-9]+]], $[[I32767]], $4
[all …]
Dsetne.ll17 ; 16: sltu ${{[0-9]+}}, $[[REGISTER]]
Dsetult.ll18 ; 16: sltu ${{[0-9]+}}, ${{[0-9]+}}
Dsetugt.ll18 ; 16: sltu ${{[0-9]+}}, ${{[0-9]+}}
Ddagcombine_crash.ll11 ; CHECK: sltu ${{[0-9]*}}, ${{[0-9]*}}, ${{[0-9]*}}
Dsetule.ll18 ; 16: sltu ${{[0-9]+}}, ${{[0-9]+}}
/external/llvm/test/CodeGen/Mips/llvm-ir/
Dadd.ll85 ; GP32: sltu $[[T0:[0-9]+]], $3, $7
101 ; GP32: sltu $[[T2:[0-9]+]], $[[T1]], $[[T0]]
105 ; GP32: sltu $[[T6:[0-9]+]], $[[T5]], $[[T3]]
110 ; GP32: sltu $[[T10:[0-9]+]], $3, $[[T7]]
117 ; GP64: sltu $[[T0:[0-9]+]], $3, $7
Dsub.ll85 ; GP32: sltu $[[T0:[0-9]+]], $5, $7
100 ; GP32: sltu $[[T1:[0-9]+]], $5, $[[T0]]
107 ; GP32: sltu $[[T8:[0-9]+]], $6, $[[T4]]
110 ; GP32: sltu $[[T10:[0-9]+]], $7, $[[T5]]
116 ; GP64: sltu $[[T0:[0-9]+]], $5, $7
/external/llvm/test/MC/Mips/
Dmips_gprel16.s35 sltu $2, $zero, $1
59 sltu $2, $zero, $1
Dmicromips-alu-instructions.s24 # CHECK-EL: sltu $3, $3, $5 # encoding: [0xa3,0x00,0x90,0x1b]
61 # CHECK-EB: sltu $3, $3, $5 # encoding: [0x00,0xa3,0x1b,0x90]
96 sltu $3, $3, $5
Dmips-alu-instructions.s27 # CHECK: sltu $3, $3, $5 # encoding: [0x2b,0x18,0x65,0x00]
58 sltu $3, $3, $5
Dmips64-alu-instructions.s25 # CHECK: sltu $3, $3, $5 # encoding: [0x2b,0x18,0x65,0x00]
53 sltu $3, $3, $5
/external/valgrind/none/tests/mips32/
DMIPS32int.stdout.exp-mips32-BE785 sltu $t0, $t1, $t2 :: rd 0x00000001 rs 0x31415927, rt 0xffffffff
786 sltu $t0, $t1, $t2 :: rd 0x00000001 rs 0x31415927, rt 0xee00ee00
787 sltu $t0, $t1, $t2 :: rd 0x00000001 rs 0x00000000, rt 0x000000ff
788 sltu $t0, $t1, $t2 :: rd 0x00000000 rs 0xffffffff, rt 0x00000000
789 sltu $t0, $t1, $t2 :: rd 0x00000001 rs 0x00000000, rt 0x00000001
790 sltu $t0, $t1, $t2 :: rd 0x00000000 rs 0x00000000, rt 0x00000000
791 sltu $t0, $t1, $t2 :: rd 0x00000001 rs 0x80000000, rt 0xffffffff
792 sltu $t0, $t1, $t2 :: rd 0x00000000 rs 0x80000000, rt 0x80000000
793 sltu $t0, $t1, $t2 :: rd 0x00000000 rs 0x7fffffff, rt 0x00000000
794 sltu $t0, $t1, $t2 :: rd 0x00000000 rs 0x80000000, rt 0x80000000
[all …]
DMIPS32int.stdout.exp-mips32-LE785 sltu $t0, $t1, $t2 :: rd 0x00000001 rs 0x31415927, rt 0xffffffff
786 sltu $t0, $t1, $t2 :: rd 0x00000001 rs 0x31415927, rt 0xee00ee00
787 sltu $t0, $t1, $t2 :: rd 0x00000001 rs 0x00000000, rt 0x000000ff
788 sltu $t0, $t1, $t2 :: rd 0x00000000 rs 0xffffffff, rt 0x00000000
789 sltu $t0, $t1, $t2 :: rd 0x00000001 rs 0x00000000, rt 0x00000001
790 sltu $t0, $t1, $t2 :: rd 0x00000000 rs 0x00000000, rt 0x00000000
791 sltu $t0, $t1, $t2 :: rd 0x00000001 rs 0x80000000, rt 0xffffffff
792 sltu $t0, $t1, $t2 :: rd 0x00000000 rs 0x80000000, rt 0x80000000
793 sltu $t0, $t1, $t2 :: rd 0x00000000 rs 0x7fffffff, rt 0x00000000
794 sltu $t0, $t1, $t2 :: rd 0x00000000 rs 0x80000000, rt 0x80000000
[all …]
DMIPS32int.stdout.exp-mips32r2-LE1263 sltu $t0, $t1, $t2 :: rd 0x00000001 rs 0x31415927, rt 0xffffffff
1264 sltu $t0, $t1, $t2 :: rd 0x00000001 rs 0x31415927, rt 0xee00ee00
1265 sltu $t0, $t1, $t2 :: rd 0x00000001 rs 0x00000000, rt 0x000000ff
1266 sltu $t0, $t1, $t2 :: rd 0x00000000 rs 0xffffffff, rt 0x00000000
1267 sltu $t0, $t1, $t2 :: rd 0x00000001 rs 0x00000000, rt 0x00000001
1268 sltu $t0, $t1, $t2 :: rd 0x00000000 rs 0x00000000, rt 0x00000000
1269 sltu $t0, $t1, $t2 :: rd 0x00000001 rs 0x80000000, rt 0xffffffff
1270 sltu $t0, $t1, $t2 :: rd 0x00000000 rs 0x80000000, rt 0x80000000
1271 sltu $t0, $t1, $t2 :: rd 0x00000000 rs 0x7fffffff, rt 0x00000000
1272 sltu $t0, $t1, $t2 :: rd 0x00000000 rs 0x80000000, rt 0x80000000
[all …]
DMIPS32int.stdout.exp-mips32r2-BE1263 sltu $t0, $t1, $t2 :: rd 0x00000001 rs 0x31415927, rt 0xffffffff
1264 sltu $t0, $t1, $t2 :: rd 0x00000001 rs 0x31415927, rt 0xee00ee00
1265 sltu $t0, $t1, $t2 :: rd 0x00000001 rs 0x00000000, rt 0x000000ff
1266 sltu $t0, $t1, $t2 :: rd 0x00000000 rs 0xffffffff, rt 0x00000000
1267 sltu $t0, $t1, $t2 :: rd 0x00000001 rs 0x00000000, rt 0x00000001
1268 sltu $t0, $t1, $t2 :: rd 0x00000000 rs 0x00000000, rt 0x00000000
1269 sltu $t0, $t1, $t2 :: rd 0x00000001 rs 0x80000000, rt 0xffffffff
1270 sltu $t0, $t1, $t2 :: rd 0x00000000 rs 0x80000000, rt 0x80000000
1271 sltu $t0, $t1, $t2 :: rd 0x00000000 rs 0x7fffffff, rt 0x00000000
1272 sltu $t0, $t1, $t2 :: rd 0x00000000 rs 0x80000000, rt 0x80000000
[all …]
/external/llvm/test/MC/Mips/mips1/
Dvalid.s96 … sltu $s4,$s5,$11 # CHECK: sltu $20, $21, $11 # encoding: [0x02,0xab,0xa0,0x2b]
97 … sltu $24,$25,-15531 # CHECK: sltiu $24, $25, -15531 # encoding: [0x2f,0x38,0xc3,0x55]
/external/v8/test/cctest/
Dtest-disasm-mips.cc432 COMPARE(sltu(a0, a1, a2), in TEST()
434 COMPARE(sltu(s0, s1, s2), in TEST()
436 COMPARE(sltu(t2, t3, t4), in TEST()
438 COMPARE(sltu(v0, v1, a2), in TEST()
/external/llvm/test/MC/Mips/mips2/
Dvalid.s122 … sltu $s4,$s5,$11 # CHECK: sltu $20, $21, $11 # encoding: [0x02,0xab,0xa0,0x2b]
123 … sltu $24,$25,-15531 # CHECK: sltiu $24, $25, -15531 # encoding: [0x2f,0x38,0xc3,0x55]
/external/v8/src/mips/
Dmacro-assembler-mips.cc914 sltu(rd, rs, rt.rm()); in Sltu()
922 sltu(rd, rs, at); in Sltu()
1909 sltu(scratch, r2, rs); in BranchShort()
1917 sltu(scratch, rs, r2); in BranchShort()
1926 sltu(scratch, rs, r2); in BranchShort()
1934 sltu(scratch, r2, rs); in BranchShort()
2018 sltu(scratch, r2, rs); in BranchShort()
2031 sltu(scratch, rs, r2); in BranchShort()
2045 sltu(scratch, rs, r2); in BranchShort()
2055 sltu(scratch, r2, rs); in BranchShort()
[all …]

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