| /external/llvm/test/MC/AArch64/ |
| D | neon-max-min-pairwise.s | 39 sminp v0.8b, v1.8b, v2.8b
40 sminp v0.16b, v1.16b, v2.16b
41 sminp v0.4h, v1.4h, v2.4h
42 sminp v0.8h, v1.8h, v2.8h
43 sminp v0.2s, v1.2s, v2.2s
44 sminp v0.4s, v1.4s, v2.4s
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| D | arm64-advsimd.s | 344 sminp.8b v0, v0, v0
415 ; CHECK: sminp.8b v0, v0, v0 ; encoding: [0x00,0xac,0x20,0x0e]
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| D | neon-diagnostics.s | 1146 sminp v0.2d, v1.2d, v2.2d
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| /external/llvm/test/CodeGen/AArch64/ |
| D | arm64-vmax.ll | 375 ;CHECK: sminp.8b
378 %tmp3 = call <8 x i8> @llvm.aarch64.neon.sminp.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
384 ;CHECK: sminp.16b
387 %tmp3 = call <16 x i8> @llvm.aarch64.neon.sminp.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2)
393 ;CHECK: sminp.4h
396 %tmp3 = call <4 x i16> @llvm.aarch64.neon.sminp.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
402 ;CHECK: sminp.8h
405 %tmp3 = call <8 x i16> @llvm.aarch64.neon.sminp.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2)
411 ;CHECK: sminp.2s
414 %tmp3 = call <2 x i32> @llvm.aarch64.neon.sminp.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
[all …]
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| D | arm64-sminv.ll | 28 ; CHECK: sminp.2s v[[REGNUM:[0-9]+]], v0, v0
94 ; CHECK: sminp.2s v[[REGNUM:[0-9]+]], v1, v1
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| /external/valgrind/none/tests/arm64/ |
| D | fp_and_simd.c | 3425 GEN_BINARY_TEST(sminp, 4s, 4s, 4s)
3426 GEN_BINARY_TEST(sminp, 2s, 2s, 2s)
3427 GEN_BINARY_TEST(sminp, 8h, 8h, 8h)
3428 GEN_BINARY_TEST(sminp, 4h, 4h, 4h)
3429 GEN_BINARY_TEST(sminp, 16b, 16b, 16b)
3430 GEN_BINARY_TEST(sminp, 8b, 8b, 8b)
|
| D | fp_and_simd.stdout.exp | 27587 sminp v9.4s, v7.4s, v8.4s 62d64293b1f70f355829fc5c1c01ea41 af666395554a939495259373a6a46faf af66…
27588 sminp v9.2s, v7.2s, v8.2s 474eee67a33ea30f445a5a271ce05414 25a5f35eb1ed19e2e8b1c40a0ba740e1 0000…
27589 sminp v9.8h, v7.8h, v8.8h 44a4cedae26bfe0c99360aa6270e325b 598c80c6a889985a18c461e5971c051e 80c6…
27590 sminp v9.4h, v7.4h, v8.4h 69da5e8c7658d7e2d6f17a27b496287b 79bea60c6198e653c830f7f1e3b0846b 0000…
27591 sminp v9.16b, v7.16b, v8.16b 27d27afac8c04028de9c75d99c633bba 18bf624e67753604f6a872fee9ebe1b0 b…
27592 sminp v9.8b, v7.8b, v8.8b 4d4e5f83a13caf55f02a29ca193fce41 25ef108ba05b1d8104bf1fb9ff399fb3 0000…
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| /external/llvm/test/MC/Disassembler/AArch64/ |
| D | neon-instructions.txt | 584 # CHECK: sminp v2.16b, v14.16b, v23.16b
586 # CHECK: sminp v4.8h, v12.8h, v25.8h
588 # CHECK: sminp v6.4s, v10.4s, v27.4s
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| D | arm64-advsimd.txt | 327 # CHECK: sminp.8b v0, v0, v0
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| /external/vixl/src/vixl/a64/ |
| D | simulator-a64.h | 1861 LogicVRegister sminp(VectorFormat vform,
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| D | macro-assembler-a64.h | 2141 V(sminp, Sminp) \
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| D | assembler-a64.h | 2963 void sminp(const VRegister& vd,
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| D | simulator-a64.cc | 2692 case NEON_SMINP: sminp(vf, rd, rn, rm); break; in VisitNEON3Same()
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| D | logic-a64.cc | 1375 LogicVRegister Simulator::sminp(VectorFormat vform, in sminp() function in vixl::Simulator
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| D | assembler-a64.cc | 3194 V(sminp, NEON_SMINP, vd.IsVector() && !vd.IsLaneSizeD()) \
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| /external/vixl/test/ |
| D | test-simulator-a64.cc | 3722 DEFINE_TEST_NEON_3SAME_NO2D(sminp, Basic)
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| /external/vixl/doc/ |
| D | supported-instructions.md | 3139 void sminp(const VRegister& vd,
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64InstrInfo.td | 2767 defm SMINP : SIMDThreeSameVectorBHS<0,0b10101,"sminp", int_aarch64_neon_sminp>;
|