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/external/llvm/test/CodeGen/Mips/msa/
D3r_splat.ll1 ; Test the MSA splat intrinsics that are encoded with the 3R instruction
15 %1 = tail call <16 x i8> @llvm.mips.splat.b(<16 x i8> %0, i32 %a)
20 declare <16 x i8> @llvm.mips.splat.b(<16 x i8>, i32) nounwind
26 ; MIPS32-DAG: splat.b [[R4:\$w[0-9]+]], [[R3]][$4]
36 %1 = tail call <8 x i16> @llvm.mips.splat.h(<8 x i16> %0, i32 %a)
41 declare <8 x i16> @llvm.mips.splat.h(<8 x i16>, i32) nounwind
47 ; MIPS32-DAG: splat.h [[R4:\$w[0-9]+]], [[R3]][$4]
57 %1 = tail call <4 x i32> @llvm.mips.splat.w(<4 x i32> %0, i32 %a)
62 declare <4 x i32> @llvm.mips.splat.w(<4 x i32>, i32) nounwind
68 ; MIPS32-DAG: splat.w [[R4:\$w[0-9]+]], [[R3]][$4]
[all …]
Dllvm-stress-s2501752154-simplified.ll9 ; splat, but then proceeded to legalize the undef's to zero, leaving it as a
10 ; non-splat that cannot be selected. It should have eliminated the undef's by
11 ; rewriting the splat constant.
Dllvm-stress-s449609655-simplified.ll11 ; isVSplat() returned the splat value for <i8 -1, i8 -1, ...> as a 32-bit APInt
12 ; (255), but the zeroinitializer splat value as an 8-bit APInt (0). The
Dllvm-stress-s2090927243-simplified.ll8 ; splat, but are legalized to zero if left in the DAG which changes the constant
9 ; into a non-splat.
Dbasic_operations.ll417 ; MIPS32-AE-DAG: splat.b $w[[R3:[0-9]+]], [[R1]]{{\[}}[[IDX]]]
441 ; MIPS32-AE-DAG: splat.h $w[[R3:[0-9]+]], [[R1]]{{\[}}[[IDX]]]
464 ; MIPS32-AE-DAG: splat.w $w[[R3:[0-9]+]], [[R1]]{{\[}}[[IDX]]]
487 ; MIPS32-AE-DAG: splat.w $w[[R3:[0-9]+]], [[R1]]{{\[}}[[IDX]]]
489 ; MIPS32-AE-DAG: splat.w $w[[R4:[0-9]+]], [[R1]]{{\[}}[[IDX]]]
513 ; MIPS32-AE-DAG: splat.b $w[[R3:[0-9]+]], [[R1]]{{\[}}[[IDX]]]
537 ; MIPS32-AE-DAG: splat.h $w[[R3:[0-9]+]], [[R1]]{{\[}}[[IDX]]]
560 ; MIPS32-AE-DAG: splat.w $w[[R3:[0-9]+]], [[R1]]{{\[}}[[IDX]]]
583 ; MIPS32-AE-DAG: splat.w $w[[R3:[0-9]+]], [[R1]]{{\[}}[[IDX]]]
585 ; MIPS32-AE-DAG: splat.w $w[[R4:[0-9]+]], [[R1]]{{\[}}[[IDX]]]
/external/llvm/test/CodeGen/X86/
Davx2-vbroadcast.ll359 ; These tests check that a vbroadcast instruction is used when we have a splat
436 %splat.splatinsert = insertelement <16 x i8> undef, i8 %tmp2, i32 0
437 …%splat.splat = shufflevector <16 x i8> %splat.splatinsert, <16 x i8> undef, <16 x i32> zeroinitial…
438 %tmp3 = bitcast <16 x i8> %splat.splat to <2 x i64>
455 %splat.splatinsert = insertelement <32 x i8> undef, i8 %tmp2, i32 0
456 …%splat.splat = shufflevector <32 x i8> %splat.splatinsert, <32 x i8> undef, <32 x i32> zeroinitial…
457 %tmp3 = bitcast <32 x i8> %splat.splat to <4 x i64>
474 %splat.splatinsert = insertelement <8 x i16> undef, i16 %tmp2, i32 0
475 …%splat.splat = shufflevector <8 x i16> %splat.splatinsert, <8 x i16> undef, <8 x i32> zeroinitiali…
476 %tmp3 = bitcast <8 x i16> %splat.splat to <2 x i64>
[all …]
Dsplat-const.ll19 %splat = shufflevector <4 x i32> %zero, <4 x i32> undef, <4 x i32> zeroinitializer
20 ret <4 x i32> %splat
38 %splat = shufflevector <4 x i32> %const, <4 x i32> undef, <4 x i32> zeroinitializer
39 ret <4 x i32> %splat
Dshl-i64.ll16 %splat = shufflevector <4 x i64> %3, <4 x i64> undef, <4 x i32> zeroinitializer
17 %shl = shl <4 x i64> %0, %splat
Dsplat-for-size.ll5 ; for size optimization using splat ops available with AVX and AVX2.
44 ; AVX can't do integer splats, so fake it: use vmovddup to splat 64-bit value.
56 ; and then we fake it: use vmovddup to splat 64-bit value.
69 ; AVX can't do integer splats, so fake it: use vbroadcastss to splat 32-bit value.
80 ; AVX can't do integer splats, so fake it: use vbroadcastss to splat 32-bit value.
Dselectiondag-crash.ll4 ; a splat mask into a constant build_vector.
Dvshift-5.ll3 ; When loading the shift amount from memory, avoid generating the splat.
/external/llvm/test/CodeGen/ARM/
Dvdup.ll336 ; Check that an SPR splat produces a vdup.
342 %splat.splatinsert = insertelement <2 x float> undef, float %conv, i32 0
343 …%splat.splat = shufflevector <2 x float> %splat.splatinsert, <2 x float> undef, <2 x i32> zeroinit…
344 %sub = fsub <2 x float> %splat.splat, %p
352 %splat.splatinsert = insertelement <4 x float> undef, float %conv, i32 0
353 …%splat.splat = shufflevector <4 x float> %splat.splatinsert, <4 x float> undef, <4 x i32> zeroinit…
354 %sub = fsub <4 x float> %splat.splat, %p
362 %splat.splatinsert = insertelement <4 x float> undef, float %conv, i32 1
363 …%splat.splat = shufflevector <4 x float> %splat.splatinsert, <4 x float> undef, <4 x i32> <i32 1, …
364 %sub = fsub <4 x float> %splat.splat, %p
/external/llvm/test/CodeGen/R600/
Ddagcombiner-bug-illegal-vec4-int-to-fp.ll19 %splat = shufflevector <4 x float> %0, <4 x float> undef, <4 x i32> zeroinitializer
20 store <4 x float> %splat, <4 x float> addrspace(1)* %out
33 %splat = shufflevector <4 x float> %0, <4 x float> undef, <4 x i32> zeroinitializer
34 store <4 x float> %splat, <4 x float> addrspace(1)* %out
/external/skia/src/opts/
DSk4px_SSE2.h47 __m128i splat = _mm_set_epi8(15,15,15,15, 11,11,11,11, 7,7,7,7, 3,3,3,3); in alphas() local
48 return Sk16b(_mm_shuffle_epi8(this->fVec, splat)); in alphas()
53 __m128i splat = _mm_set_epi8(3,3,3,3, 2,2,2,2, 1,1,1,1, 0,0,0,0); in Load4Alphas() local
54 return Sk16b(_mm_shuffle_epi8(_mm_cvtsi32_si128(as), splat)); in Load4Alphas()
/external/antlr/antlr-3.4/runtime/Ruby/lib/antlr3/template/
Dparameter.rb9 elsif splat then "*#{ name }"
40 param.splat = options.fetch( :splat, false )
/external/llvm/test/Transforms/InstCombine/
Dvec_extract_elt.ll13 %splat = shufflevector <8 x i64> %vec, <8 x i64> undef, <8 x i32> zeroinitializer
14 %add = add <8 x i64> %splat, <i64 0, i64 1, i64 2, i64 3, i64 4, i64 5, i64 6, i64 7>
/external/llvm/test/CodeGen/PowerPC/
Dctrloop-fp64.ll37 …%broadcast.splat.i = shufflevector <2 x i64> %broadcast.splatinsert.i, <2 x i64> undef, <2 x i32> …
44 store <2 x i64> %broadcast.splat.i, <2 x i64>* %1, align 8
48 store <2 x i64> %broadcast.splat.i, <2 x i64>* %3, align 8
Dvec_extload.ll22 ; The zero extend uses a more clever logic: a vector splat
45 ; with a splat, loads it from memory.
Dqpx-bv-sint.ll24 ; FIXME: We could 'promote' this to a vector earlier and remove this splat.
Dvec_add_sub_doubleword.ll37 ; up the vector register). Instead, it would be better to splat
/external/llvm/lib/Target/Mips/
DMSA.txt30 When the shuffle description describes a splat operation, splat.[bhwd]
43 splat.[bhwd]
/external/llvm/test/MC/Disassembler/Hexagon/
Dxtype_perm.txt70 # Vector splat bytes
74 # Vector splat halfwords
/external/clang/include/clang/Basic/
Darm_neon.td98 // splat - Take a vector and a lane index, and return a vector of the same type
100 // example: (splat $p0, $p1) ->
103 def splat;
244 // a: scalar of element type (splat to vector type)
353 def OP_MUL_LN : Op<(op "*", $p0, (splat $p1, $p2))>;
354 def OP_MULX_LN : Op<(call "vmulx", $p0, (splat $p1, $p2))>;
355 def OP_MULL_LN : Op<(call "vmull", $p0, (splat $p1, $p2))>;
356 def OP_MULLHi_LN: Op<(call "vmull", (call "vget_high", $p0), (splat $p1, $p2))>;
357 def OP_MLA_LN : Op<(op "+", $p0, (op "*", $p1, (splat $p2, $p3)))>;
358 def OP_MLS_LN : Op<(op "-", $p0, (op "*", $p1, (splat $p2, $p3)))>;
[all …]
/external/llvm/test/MC/Mips/msa/
Dtest_3r.s201 # CHECK: splat.b $w28, $w1[$1] # encoding: [0x78,0x81,0x0f,0x14]
202 # CHECK: splat.h $w2, $w11[$11] # encoding: [0x78,0xab,0x58,0x94]
203 # CHECK: splat.w $w22, $w0[$11] # encoding: [0x78,0xcb,0x05,0x94]
204 # CHECK: splat.d $w0, $w0[$2] # encoding: [0x78,0xe2,0x00,0x14]
444 splat.b $w28, $w1[$1]
445 splat.h $w2, $w11[$11]
446 splat.w $w22, $w0[$11]
447 splat.d $w0, $w0[$2]
/external/llvm/test/CodeGen/AArch64/
Darm64-setcc-int-to-fp-combine.ll29 ; Fold explicit AND operations when the constant isn't a splat of a single

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