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Searched refs:sqdmulh (Results 1 – 21 of 21) sorted by relevance

/external/llvm/test/MC/AArch64/
Dneon-scalar-by-elem-saturating-mul.s27 sqdmulh h0, h1, v0.h[0]
28 sqdmulh h10, h11, v10.h[4]
29 sqdmulh h20, h21, v15.h[7]
30 sqdmulh s25, s26, v27.s[3]
31 sqdmulh s2, s6, v7.s[0]
Dneon-mul-div-instructions.s57 sqdmulh v2.4h, v25.4h, v3.4h
58 sqdmulh v12.8h, v5.8h, v13.8h
59 sqdmulh v3.2s, v1.2s, v30.2s
Dneon-scalar-mul.s9 sqdmulh h10, h11, h12
10 sqdmulh s20, s21, s2
Dneon-2velem.s245 sqdmulh v0.4h, v1.4h, v2.h[2]
246 sqdmulh v0.8h, v1.8h, v2.h[2]
247 sqdmulh v0.2s, v1.2s, v2.s[2]
248 sqdmulh v0.2s, v1.2s, v22.s[2]
249 sqdmulh v0.4s, v1.4s, v2.s[2]
250 sqdmulh v0.4s, v1.4s, v22.s[2]
Dneon-diagnostics.s887 sqdmulh h10, s11, h12
888 sqdmulh s20, h21, s2
1243 sqdmulh v2.4h, v25.8h, v3.4h
1244 sqdmulh v12.2d, v5.2d, v13.2d
1245 sqdmulh v3.8b, v1.8b, v30.8b
3633 sqdmulh v0.4h, v1.4h, v2.h[8]
3634 sqdmulh v0.4h, v1.4h, v16.h[2]
3635 sqdmulh v0.8h, v1.8h, v2.h[8]
3636 sqdmulh v0.8h, v1.8h, v16.h[2]
3637 sqdmulh v0.2s, v1.2s, v2.s[4]
[all …]
Darm64-advsimd.s347 sqdmulh.4h v0, v0, v0
418 ; CHECK: sqdmulh.4h v0, v0, v0 ; encoding: [0x00,0xb4,0x60,0x0e]
994 sqdmulh.h h0, h0, v0[7]
995 sqdmulh.s s0, s0, v0[3]
1012 ; CHECK: sqdmulh.h h0, h0, v0[7] ; encoding: [0x00,0xc8,0x70,0x5f]
1013 ; CHECK: sqdmulh.s s0, s0, v0[3] ; encoding: [0x00,0xc8,0xa0,0x5f]
1098 sqdmulh.4h v0, v0, v0[0]
1099 sqdmulh.8h v0, v0, v0[1]
1100 sqdmulh.2s v0, v0, v0[2]
1101 sqdmulh.4s v0, v0, v0[3]
[all …]
/external/llvm/test/CodeGen/AArch64/
Darm64-neon-mul-div.ll704 declare <4 x i16> @llvm.aarch64.neon.sqdmulh.v4i16(<4 x i16>, <4 x i16>)
705 declare <8 x i16> @llvm.aarch64.neon.sqdmulh.v8i16(<8 x i16>, <8 x i16>)
706 declare <2 x i32> @llvm.aarch64.neon.sqdmulh.v2i32(<2 x i32>, <2 x i32>)
707 declare <4 x i32> @llvm.aarch64.neon.sqdmulh.v4i32(<4 x i32>, <4 x i32>)
711 %prod = call <4 x i16> @llvm.aarch64.neon.sqdmulh.v4i16(<4 x i16> %lhs, <4 x i16> %rhs)
712 ; CHECK: sqdmulh v0.4h, v0.4h, v1.4h
718 %prod = call <8 x i16> @llvm.aarch64.neon.sqdmulh.v8i16(<8 x i16> %lhs, <8 x i16> %rhs)
719 ; CHECK: sqdmulh v0.8h, v0.8h, v1.8h
725 %prod = call <2 x i32> @llvm.aarch64.neon.sqdmulh.v2i32(<2 x i32> %lhs, <2 x i32> %rhs)
726 ; CHECK: sqdmulh v0.2s, v0.2s, v1.2s
[all …]
Darm64-vmul.ll123 ;CHECK: sqdmulh.4h
126 %tmp3 = call <4 x i16> @llvm.aarch64.neon.sqdmulh.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
132 ;CHECK: sqdmulh.8h
135 %tmp3 = call <8 x i16> @llvm.aarch64.neon.sqdmulh.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2)
141 ;CHECK: sqdmulh.2s
144 %tmp3 = call <2 x i32> @llvm.aarch64.neon.sqdmulh.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
150 ;CHECK: sqdmulh.4s
153 %tmp3 = call <4 x i32> @llvm.aarch64.neon.sqdmulh.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2)
159 ;CHECK: sqdmulh s0, {{s[0-9]+}}, {{s[0-9]+}}
162 %tmp3 = call i32 @llvm.aarch64.neon.sqdmulh.i32(i32 %tmp1, i32 %tmp2)
[all …]
Darm64-neon-2velem.ll17 declare <4 x i32> @llvm.aarch64.neon.sqdmulh.v4i32(<4 x i32>, <4 x i32>)
19 declare <2 x i32> @llvm.aarch64.neon.sqdmulh.v2i32(<2 x i32>, <2 x i32>)
21 declare <8 x i16> @llvm.aarch64.neon.sqdmulh.v8i16(<8 x i16>, <8 x i16>)
23 declare <4 x i16> @llvm.aarch64.neon.sqdmulh.v4i16(<4 x i16>, <4 x i16>)
1278 …%vqdmulh2.i = tail call <4 x i16> @llvm.aarch64.neon.sqdmulh.v4i16(<4 x i16> %a, <4 x i16> %shuffl…
1288 …%vqdmulh2.i = tail call <8 x i16> @llvm.aarch64.neon.sqdmulh.v8i16(<8 x i16> %a, <8 x i16> %shuffl…
1298 …%vqdmulh2.i = tail call <2 x i32> @llvm.aarch64.neon.sqdmulh.v2i32(<2 x i32> %a, <2 x i32> %shuffl…
1308 …%vqdmulh2.i = tail call <4 x i32> @llvm.aarch64.neon.sqdmulh.v4i32(<4 x i32> %a, <4 x i32> %shuffl…
2657 …%vqdmulh2.i = tail call <4 x i16> @llvm.aarch64.neon.sqdmulh.v4i16(<4 x i16> %a, <4 x i16> %shuffl…
2667 …%vqdmulh2.i = tail call <8 x i16> @llvm.aarch64.neon.sqdmulh.v8i16(<8 x i16> %a, <8 x i16> %shuffl…
[all …]
/external/llvm/test/MC/Disassembler/AArch64/
Dneon-instructions.txt657 # CHECK: sqdmulh v31.2s, v31.2s, v31.2s
658 # CHECK: sqdmulh v5.4s, v7.4s, v9.4s
1475 # CHECK: sqdmulh h10, h11, h12
1476 # CHECK: sqdmulh s20, s21, s2
2426 # CHECK: sqdmulh h7, h1, v14.h[0]
2427 # CHECK: sqdmulh h7, h15, v8.h[1]
2428 # CHECK: sqdmulh h7, h15, v8.h[2]
2429 # CHECK: sqdmulh h7, h15, v8.h[3]
2430 # CHECK: sqdmulh h7, h15, v8.h[4]
2431 # CHECK: sqdmulh h7, h15, v8.h[5]
[all …]
Darm64-advsimd.txt330 # CHECK: sqdmulh.4h v0, v0, v0
1610 # CHECK: sqdmulh.h h0, h0, v0[7]
1611 # CHECK: sqdmulh.s s0, s0, v0[3]
1734 # CHECK: sqdmulh.4h v0, v0, v0[0]
1735 # CHECK: sqdmulh.8h v0, v0, v0[1]
1736 # CHECK: sqdmulh.2s v0, v0, v0[2]
1737 # CHECK: sqdmulh.4s v0, v0, v0[3]
/external/vixl/test/
Dtest-simulator-a64.cc3723 DEFINE_TEST_NEON_3SAME_HS(sqdmulh, Basic)
3792 DEFINE_TEST_NEON_3SAME_SCALAR_HS(sqdmulh, Basic)
4059 DEFINE_TEST_NEON_BYELEMENT(sqdmulh, Basic, Basic, Basic)
4076 DEFINE_TEST_NEON_BYELEMENT_SCALAR(sqdmulh, Basic, Basic, Basic)
/external/valgrind/none/tests/arm64/
Dfp_and_simd.stdout.exp28027 sqdmulh s0, s1, v2.s[1] 3d7e7992f1bb427fdd73346228ce7f21 20d6c16e8b88e169a1c1d8ea166021bd c1ccb…
28028 sqdmulh s0, s1, v2.s[3] d29d89331382a5ebe2391c401e1c3953 492d26b1cdeacfed15d8a4894ecbfe4d f718f…
28029 sqdmulh h0, h1, v2.h[2] f52116c199ced952b99cfe5e6c9971c1 96182fe1a820548a31fbd1a556f25e76 67a69…
28030 sqdmulh h0, h1, v2.h[7] 0a293f71e27d93737b3f433370aae5ed 1408d50cde10a1b5df5c29e61e3f2e20 80ec0…
28035 sqdmulh v0.4s, v1.4s, v2.s[1] 542a7e434b6b7d9a5a7fa4b15bc80297 af7fcf294d97828e6e664259fa86eb02 …
28036 sqdmulh v0.4s, v1.4s, v2.s[3] acb0e78fb148450af6194a7a0bbb272b ae21815da7b388190eb641a741b96677 …
28037 sqdmulh v0.2s, v1.2s, v2.s[1] 08f386627482158cdeaaa41a0cb30112 49ae8f15947b5dd6cf6b590a4f809c9e …
28038 sqdmulh v0.2s, v1.2s, v2.s[3] 6f86be2f576e115694459485a3863401 83bb5dc6d64125f734976e7669b0322a …
28039 sqdmulh v0.8h, v1.8h, v2.h[2] e3fff56b1e5f5e999cfdffb0120865ac 61da4ee2325c02b0c25064dfd11ccbd1 …
28040 sqdmulh v0.8h, v1.8h, v2.h[7] 68f18d888daa1f8c7be8ca8e9f0c37c6 e6a0c8df6d1e1a37fca81f3acd990c45 …
[all …]
/external/vixl/src/vixl/a64/
Dsimulator-a64.cc2708 case NEON_SQDMULH: sqdmulh(vf, rd, rn, rm); break; in VisitNEON3Same()
2870 case NEON_SQDMULH_byelement: Op = &Simulator::sqdmulh; vf = vf_r; break; in VisitNEONByIndexedElement()
3577 case NEON_SQDMULH_scalar: sqdmulh(vf, rd, rn, rm); break; in VisitNEONScalar3Same()
3637 Op = &Simulator::sqdmulh; in VisitNEONScalarByIndexedElement()
Dsimulator-a64.h1705 LogicVRegister sqdmulh(VectorFormat vform,
2258 LogicVRegister sqdmulh(VectorFormat vform,
Dmacro-assembler-a64.h2153 V(sqdmulh, Sqdmulh) \
2334 V(sqdmulh, Sqdmulh) \
Dassembler-a64.h3444 void sqdmulh(const VRegister& vd,
3454 void sqdmulh(const VRegister& vd,
Dlogic-a64.cc1079 LogicVRegister Simulator::sqdmulh(VectorFormat vform, in sqdmulh() function in vixl::Simulator
1086 return sqdmulh(vform, dst, src1, dup_element(indexform, temp, src2, index)); in sqdmulh()
3295 LogicVRegister Simulator::sqdmulh(VectorFormat vform, in sqdmulh() function in vixl::Simulator
Dassembler-a64.cc3183 V(sqdmulh, NEON_SQDMULH, vd.IsLaneSizeH() || vd.IsLaneSizeS()) \
3495 V(sqdmulh, NEON_SQDMULH_byelement, true) \
/external/vixl/doc/
Dsupported-instructions.md3372 void sqdmulh(const VRegister& vd,
3382 void sqdmulh(const VRegister& vd,
/external/llvm/lib/Target/AArch64/
DAArch64InstrInfo.td2770 defm SQDMULH : SIMDThreeSameVectorHS<0,0b10110,"sqdmulh",int_aarch64_neon_sqdmulh>;
3001 defm SQDMULH : SIMDThreeScalarHS< 0, 0b10110, "sqdmulh", int_aarch64_neon_sqdmulh>;
4342 defm SQDMULH : SIMDIndexedHS<0, 0b1100, "sqdmulh", int_aarch64_neon_sqdmulh>;