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Searched refs:sqdmull (Results 1 – 23 of 23) sorted by relevance

/external/llvm/test/MC/AArch64/
Dneon-scalar-by-elem-saturating-mul.s6 sqdmull s1, h1, v1.h[1]
7 sqdmull s8, h2, v5.h[2]
8 sqdmull s12, h17, v9.h[3]
9 sqdmull s31, h31, v15.h[7]
10 sqdmull d1, s1, v4.s[0] define
11 sqdmull d31, s31, v31.s[3]
12 sqdmull d9, s10, v15.s[0] define
Dneon-scalar-mul.s59 sqdmull s12, h22, h12
60 sqdmull d15, s22, s12
Dneon-2velem.s231 sqdmull v0.4s, v1.4h, v2.h[2]
232 sqdmull v0.2d, v1.2s, v2.s[2]
233 sqdmull v0.2d, v1.2s, v22.s[2]
Dneon-diagnostics.s2558 sqdmull v0.4s, v1.4s, v2.4h
2559 sqdmull v0.2d, v1.2d, v2.2s
2579 sqdmull v0.8h, v1.8b, v2.8b
3583 sqdmull v0.4h, v1.4h, v2.h[2]
3584 sqdmull v0.4s, v1.4h, v2.h[8]
3585 sqdmull v0.4s, v1.4h, v16.h[4]
3586 sqdmull v0.2s, v1.2s, v2.s[2]
3587 sqdmull v0.2d, v1.2s, v2.s[4]
3588 sqdmull v0.2d, v1.2s, v22.s[4]
4839 sqdmull s12, h22, s12
[all …]
Darm64-advsimd.s996 sqdmull.h s0, h0, v0[7]
997 sqdmull.s d0, s0, v0[3]
1014 ; CHECK: sqdmull.h s0, h0, v0[7] ; encoding: [0x00,0xb8,0x70,0x5f]
1015 ; CHECK: sqdmull.s d0, s0, v0[3] ; encoding: [0x00,0xb8,0xa0,0x5f]
1102 sqdmull.4s v0, v0, v0[0]
1104 sqdmull.2d v0, v0, v0[2]
1171 ; CHECK: sqdmull.4s v0, v0, v0[0] ; encoding: [0x00,0xb0,0x40,0x0f]
1173 ; CHECK: sqdmull.2d v0, v0, v0[2] ; encoding: [0x00,0xb8,0x80,0x0f]
1834 sqdmull s0, h0, h0
1835 sqdmull d0, s0, s0 define
[all …]
Dneon-3vdiff.s269 sqdmull v0.4s, v1.4h, v2.4h
270 sqdmull v0.2d, v1.2s, v2.2s
/external/llvm/test/CodeGen/AArch64/
Dmachine-copy-prop.ll32 …%sqdmull = tail call <4 x i32> @llvm.aarch64.neon.sqdmull.v4i32(<4 x i16> <i16 1, i16 0, i16 0, i1…
33 …= tail call <4 x i32> @llvm.aarch64.neon.sqadd.v4i32(<4 x i32> zeroinitializer, <4 x i32> %sqdmull)
85 declare <4 x i32> @llvm.aarch64.neon.sqdmull.v4i32(<4 x i16>, <4 x i16>)
Darm64-vmul.ll68 ;CHECK: sqdmull.4s
71 %tmp3 = call <4 x i32> @llvm.aarch64.neon.sqdmull.v4i32(<4 x i16> %tmp1, <4 x i16> %tmp2)
77 ;CHECK: sqdmull.2d
80 %tmp3 = call <2 x i64> @llvm.aarch64.neon.sqdmull.v2i64(<2 x i32> %tmp1, <2 x i32> %tmp2)
91 %tmp3 = call <4 x i32> @llvm.aarch64.neon.sqdmull.v4i32(<4 x i16> %tmp1, <4 x i16> %tmp2)
102 %tmp3 = call <2 x i64> @llvm.aarch64.neon.sqdmull.v2i64(<2 x i32> %tmp1, <2 x i32> %tmp2)
107 declare <4 x i32> @llvm.aarch64.neon.sqdmull.v4i32(<4 x i16>, <4 x i16>) nounwind readnone
108 declare <2 x i64> @llvm.aarch64.neon.sqdmull.v2i64(<2 x i32>, <2 x i32>) nounwind readnone
309 %tmp4 = call <4 x i32> @llvm.aarch64.neon.sqdmull.v4i32(<4 x i16> %tmp1, <4 x i16> %tmp2)
320 %tmp4 = call <2 x i64> @llvm.aarch64.neon.sqdmull.v2i64(<2 x i32> %tmp1, <2 x i32> %tmp2)
[all …]
Darm64-neon-2velem-high.ll7 declare <2 x i64> @llvm.aarch64.neon.sqdmull.v2i64(<2 x i32>, <2 x i32>)
11 declare <4 x i32> @llvm.aarch64.neon.sqdmull.v4i32(<4 x i16>, <4 x i16>)
89 …%vqdmull15.i.i = tail call <4 x i32> @llvm.aarch64.neon.sqdmull.v4i32(<4 x i16> %shuffle.i.i, <4 x…
101 …%vqdmull9.i.i = tail call <2 x i64> @llvm.aarch64.neon.sqdmull.v2i64(<2 x i32> %shuffle.i.i, <2 x …
170 …%vqdmlal15.i.i = tail call <4 x i32> @llvm.aarch64.neon.sqdmull.v4i32(<4 x i16> %shuffle.i.i, <4 x…
182 …%vqdmlal9.i.i = tail call <2 x i64> @llvm.aarch64.neon.sqdmull.v2i64(<2 x i32> %shuffle.i.i, <2 x …
248 …%vqdmlsl15.i.i = tail call <4 x i32> @llvm.aarch64.neon.sqdmull.v4i32(<4 x i16> %shuffle.i.i, <4 x…
260 …%vqdmlsl9.i.i = tail call <2 x i64> @llvm.aarch64.neon.sqdmull.v2i64(<2 x i32> %shuffle.i.i, <2 x …
Darm64-neon-2velem.ll25 declare <2 x i64> @llvm.aarch64.neon.sqdmull.v2i64(<2 x i32>, <2 x i32>)
27 declare <4 x i32> @llvm.aarch64.neon.sqdmull.v4i32(<4 x i16>, <4 x i16>)
1102 …%vqdmlal2.i = tail call <4 x i32> @llvm.aarch64.neon.sqdmull.v4i32(<4 x i16> %b, <4 x i16> %shuffl…
1113 …%vqdmlal2.i = tail call <2 x i64> @llvm.aarch64.neon.sqdmull.v2i64(<2 x i32> %b, <2 x i32> %shuffl…
1125 …%vqdmlal2.i = tail call <4 x i32> @llvm.aarch64.neon.sqdmull.v4i32(<4 x i16> %shuffle.i, <4 x i16>…
1137 …%vqdmlal2.i = tail call <2 x i64> @llvm.aarch64.neon.sqdmull.v2i64(<2 x i32> %shuffle.i, <2 x i32>…
1148 …%vqdmlsl2.i = tail call <4 x i32> @llvm.aarch64.neon.sqdmull.v4i32(<4 x i16> %b, <4 x i16> %shuffl…
1159 …%vqdmlsl2.i = tail call <2 x i64> @llvm.aarch64.neon.sqdmull.v2i64(<2 x i32> %b, <2 x i32> %shuffl…
1171 …%vqdmlsl2.i = tail call <4 x i32> @llvm.aarch64.neon.sqdmull.v4i32(<4 x i16> %shuffle.i, <4 x i16>…
1183 …%vqdmlsl2.i = tail call <2 x i64> @llvm.aarch64.neon.sqdmull.v2i64(<2 x i32> %shuffle.i, <2 x i32>…
[all …]
Darm64-neon-3vdiff.ll5 declare <2 x i64> @llvm.aarch64.neon.sqdmull.v2i64(<2 x i32>, <2 x i32>)
9 declare <4 x i32> @llvm.aarch64.neon.sqdmull.v4i32(<4 x i16>, <4 x i16>)
1675 ; CHECK: sqdmull {{v[0-9]+}}.4s, {{v[0-9]+}}.4h, {{v[0-9]+}}.4h
1677 %vqdmull2.i = tail call <4 x i32> @llvm.aarch64.neon.sqdmull.v4i32(<4 x i16> %a, <4 x i16> %b)
1683 ; CHECK: sqdmull {{v[0-9]+}}.2d, {{v[0-9]+}}.2s, {{v[0-9]+}}.2s
1685 %vqdmull2.i = tail call <2 x i64> @llvm.aarch64.neon.sqdmull.v2i64(<2 x i32> %a, <2 x i32> %b)
1693 %vqdmlal2.i = tail call <4 x i32> @llvm.aarch64.neon.sqdmull.v4i32(<4 x i16> %b, <4 x i16> %c)
1702 %vqdmlal2.i = tail call <2 x i64> @llvm.aarch64.neon.sqdmull.v2i64(<2 x i32> %b, <2 x i32> %c)
1711 %vqdmlsl2.i = tail call <4 x i32> @llvm.aarch64.neon.sqdmull.v4i32(<4 x i16> %b, <4 x i16> %c)
1720 %vqdmlsl2.i = tail call <2 x i64> @llvm.aarch64.neon.sqdmull.v2i64(<2 x i32> %b, <2 x i32> %c)
[all …]
/external/llvm/test/MC/Disassembler/AArch64/
Dneon-instructions.txt1346 # CHECK: sqdmull v0.4s, v1.4h, v2.4h
1347 # CHECK: sqdmull v0.2d, v1.2s, v2.2s
1778 # CHECK: sqdmull s12, h22, h12
1779 # CHECK: sqdmull d15, s22, s12
2397 # CHECK: sqdmull s1, h1, v1.h[0]
2398 # CHECK: sqdmull s1, h1, v1.h[1]
2399 # CHECK: sqdmull s1, h1, v1.h[2]
2400 # CHECK: sqdmull s1, h1, v1.h[3]
2401 # CHECK: sqdmull s1, h1, v1.h[4]
2402 # CHECK: sqdmull s1, h1, v1.h[5]
[all …]
Darm64-advsimd.txt1612 # CHECK: sqdmull.h s0, h0, v0[7]
1613 # CHECK: sqdmull.s d0, s0, v0[3]
1738 # CHECK: sqdmull.4s v0, v0, v0[0]
1740 # CHECK: sqdmull.2d v0, v0, v0[2]
2291 # CHECK: sqdmull s0, h0, h0
2292 # CHECK: sqdmull d0, s0, s0
/external/vixl/src/vixl/a64/
Dlogic-a64.cc1007 LogicVRegister Simulator::sqdmull(VectorFormat vform, in sqdmull() function in vixl::Simulator
1015 return sqdmull(vform, dst, src1, dup_element(indexform, temp, src2, index)); in sqdmull()
3210 LogicVRegister product = sqdmull(vform, temp, src1, src2); in sqdmlal()
3230 LogicVRegister product = sqdmull(vform, temp, src1, src2); in sqdmlsl()
3245 LogicVRegister Simulator::sqdmull(VectorFormat vform, in sqdmull() function in vixl::Simulator
Dsimulator-a64.cc2789 case NEON_SQDMULL: sqdmull(vf_l, rd, rn, rm); break; in VisitNEON3Different()
2918 Op = &Simulator::sqdmull; in VisitNEONByIndexedElement()
3535 case NEON_SQDMULL_scalar: sqdmull(vf, rd, rn, rm); break; in VisitNEONScalar3Diff()
3633 case NEON_SQDMULL_byelement_scalar: Op = &Simulator::sqdmull; break; in VisitNEONScalarByIndexedElement()
Dsimulator-a64.h1675 LogicVRegister sqdmull(VectorFormat vform,
2297 V(sqdmull) \
Dmacro-assembler-a64.h2154 V(sqdmull, Sqdmull) \
2336 V(sqdmull, Sqdmull) \
Dassembler-a64.h2377 void sqdmull(const VRegister& vd,
3434 void sqdmull(const VRegister& vd,
Dassembler-a64.cc2395 V(sqdmull, NEON_SQDMULL, vn.Is1H() || vn.Is1S() || vn.Is4H() || vn.Is2S()) \
3530 V(sqdmull, NEON_SQDMULL_byelement, vn.IsScalar() || vn.IsD()) \ in NEON_FPBYELEMENT_LIST()
/external/vixl/test/
Dtest-simulator-a64.cc3829 DEFINE_TEST_NEON_3DIFF_LONG_SD(sqdmull, Basic)
3847 DEFINE_TEST_NEON_3DIFF_SCALAR_LONG_SD(sqdmull, Basic)
4058 DEFINE_TEST_NEON_BYELEMENT_DIFF(sqdmull, Basic, Basic, Basic)
4075 DEFINE_TEST_NEON_BYELEMENT_DIFF_SCALAR(sqdmull, Basic, Basic, Basic)
/external/valgrind/none/tests/arm64/
Dfp_and_simd.stdout.exp27980 sqdmull d31, s30, v29.s[0] ad5e47b1e95a95f41616371096e2d8be f9a3a29022b802c8a2a5ec450d94f2ca 4d…
27981 sqdmull d31, s30, v29.s[3] 89065389a6f6b2b64dcf3b145ad6745b c3a174a1c73b0ce6822d2500bd52f269 bc…
27982 sqdmull s31, h30, v13.h[1] c982438e3da5a7d06dd4dfd62dc7d4d1 0521d05cfda032fba0efe535721a3bc0 3b…
27983 sqdmull s31, h30, v13.h[5] 71657b3472bb9577fa39084953889bd6 c6b51b35863b983b81fe10da70c17183 ce…
28001 sqdmull v29.2d, v20.2s, v3.s[0] 402db767977be3c43a7bfb50536ef05e 052e7f3f2ede17d3203ec149f2261d…
28002 sqdmull v29.2d, v20.2s, v3.s[3] 908c7c0900971f74ced838021c001a7f 1029a86e6dc9fcd66aef1247d5a7a9…
28005 sqdmull v29.4s, v20.4h, v3.h[0] dec3eadede091e0306dc7d7059497665 124626e214799c11c986f60c24134d…
28006 sqdmull v29.4s, v20.4h, v3.h[7] 257666f998fb5a5ea47165df46555635 6b4c9e837b719b3876278abf0447a6…
28013 sqdmull d0, s8, s16 0b83fb7896357e270cd4a436a555c764 972bafe46ca71991c3180a7c034ec968 988d65ddc…
28014 sqdmull s0, h8, h16 bda14f25162ca2b4156f8b9b68514697 be471132dcaef162fc2a70ffba3b7386 eca3a7405…
[all …]
/external/vixl/doc/
Dsupported-instructions.md3391 void sqdmull(const VRegister& vd,
3401 void sqdmull(const VRegister& vd,
/external/llvm/lib/Target/AArch64/
DAArch64InstrInfo.td3058 defm SQDMULL : SIMDThreeScalarMixedHS<0, 0b11010, "sqdmull",
3266 defm SQDMULL : SIMDLongThreeVectorHS<0, 0b1101, "sqdmull",
4363 defm SQDMULL : SIMDIndexedLongSD<0, 0b1011, "sqdmull", int_aarch64_neon_sqdmull>;
4371 // A scalar sqdmull with the second operand being a vector lane can be