Searched refs:src0_neg (Results 1 – 7 of 7) sorted by relevance
| /external/llvm/lib/Target/R600/ |
| D | R600InstrFormats.td | 96 bits<1> src0_neg;
99 let Word0{12} = src0_neg;
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| D | R600Instructions.td | 97 R600_Reg32:$src0, NEG:$src0_neg, REL:$src0_rel, ABS:$src0_abs, SEL:$src0_sel,
102 "$src0_neg$src0_abs$src0$src0_abs$src0_rel, "
139 R600_Reg32:$src0, NEG:$src0_neg, REL:$src0_rel, ABS:$src0_abs, SEL:$src0_sel,
145 "$src0_neg$src0_abs$src0$src0_abs$src0_rel, "
178 R600_Reg32:$src0, NEG:$src0_neg, REL:$src0_rel, SEL:$src0_sel,
184 "$src0_neg$src0$src0_rel, "
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| D | R600ExpandSpecialInstrs.cpp | 342 SetFlagInNewMI(NewMI, &MI, AMDGPU::OpName::src0_neg); in runOnMachineFunction()
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| D | R600InstrInfo.cpp | 1243 OPERAND_CASE(AMDGPU::OpName::src0_neg) in getSlotedOps()
1283 AMDGPU::OpName::src0_neg, in buildSlotOfVectorInstruction()
1371 case 0: FlagIndex = getOperandIdx(*MI, AMDGPU::OpName::src0_neg); break; in getFlagOp()
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| D | EvergreenInstructions.td | 369 let src0_neg = 0;
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| D | R600ISelLowering.cpp | 2265 TII->getOperandIdx(Opcode, AMDGPU::OpName::src0_neg), in PostISelFolding()
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| /external/mesa3d/src/gallium/drivers/r300/compiler/ |
| D | radeon_optimize.c | 567 unsigned src0_neg = inst_add->U.I.SrcReg[0].Negate & dstmask; in peephole_add_presub_add() local
582 if (inst_add->U.I.SrcReg[0].Negate && src0_neg != dstmask) in peephole_add_presub_add()
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