Searched refs:src1_neg (Results 1 – 7 of 7) sorted by relevance
| /external/llvm/lib/Target/R600/ |
| D | R600InstrFormats.td | 97 bits<1> src1_neg;
100 let Word0{25} = src1_neg;
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| D | R600ExpandSpecialInstrs.cpp | 343 SetFlagInNewMI(NewMI, &MI, AMDGPU::OpName::src1_neg); in runOnMachineFunction()
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| D | R600Instructions.td | 111 let src1_neg = 0;
140 R600_Reg32:$src1, NEG:$src1_neg, REL:$src1_rel, ABS:$src1_abs, SEL:$src1_sel,
146 "$src1_neg$src1_abs$src1$src1_abs$src1_rel, "
179 R600_Reg32:$src1, NEG:$src1_neg, REL:$src1_rel, SEL:$src1_sel,
185 "$src1_neg$src1$src1_rel, "
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| D | R600InstrInfo.cpp | 1248 OPERAND_CASE(AMDGPU::OpName::src1_neg) in getSlotedOps()
1287 AMDGPU::OpName::src1_neg, in buildSlotOfVectorInstruction()
1372 case 1: FlagIndex = getOperandIdx(*MI, AMDGPU::OpName::src1_neg); break; in getFlagOp()
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| D | EvergreenInstructions.td | 373 let src1_neg = 0;
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| D | R600ISelLowering.cpp | 2266 TII->getOperandIdx(Opcode, AMDGPU::OpName::src1_neg), in PostISelFolding()
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| /external/mesa3d/src/gallium/drivers/r300/compiler/ |
| D | radeon_optimize.c | 568 unsigned src1_neg = inst_add->U.I.SrcReg[1].Negate & dstmask; in peephole_add_presub_add() local
586 if (inst_add->U.I.SrcReg[1].Negate && src1_neg != dstmask) in peephole_add_presub_add()
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