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Searched refs:sshr (Results 1 – 25 of 34) sorted by relevance

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/external/libhevc/common/arm64/
Dihevc_intra_pred_luma_vert.s233 sshr d24, d24,#8
236 sshr d25, d25,#8
243 sshr d24, d24,#8
246 sshr d25, d25,#8
268 sshr d24, d24,#8
271 sshr d25, d25,#8
281 sshr d24, d24,#8
284 sshr d25, d25,#8
298 sshr d24, d24,#8
301 sshr d25, d25,#8
[all …]
Dihevc_intra_pred_luma_dc.s138 sshr d7, d7,#32 define
257 sshr d3, d3,#8 //row 0 shift (prol) (first value to be ignored) define
266 sshr d3, d3,#8 //row 1 shift (prol) define
275 sshr d3, d3,#8 //row 2 shift (prol) define
283 sshr d3, d3,#8 //row 3 shift (prol) define
291 sshr d3, d3,#8 //row 4 shift (prol) define
299 sshr d3, d3,#8 //row 5 shift (prol) define
310 sshr d3, d3,#8 //row 6 shift (prol) define
317 sshr d3, d3,#8 //row 7 shift (prol) define
346 sshr d3, d3,#8 //row 9 shift (prol) define
[all …]
Dihevc_intra_pred_luma_horz.s212 sshr v24.8h, v24.8h,#1
226 sshr v24.8h, v24.8h,#1
294 sshr v24.8h, v24.8h,#1
338 sshr v24.8h, v24.8h,#1
Dihevc_intra_pred_chroma_horz.s297 sshr v24.8h, v24.8h,#1
341 sshr v24.8h, v24.8h,#1
Dihevc_intra_pred_luma_mode_3_to_9.s164 sshr v22.8h, v22.8h,#5
296 sshr v12.8h, v12.8h,#5
408 sshr v14.8h, v14.8h,#5
503 sshr v22.8h, v22.8h,#5
Dihevc_intra_pred_filters_luma_mode_11_to_17.s284 sshr v22.8h, v22.8h,#5
416 sshr v12.8h, v12.8h,#5
529 sshr v14.8h, v14.8h,#5
632 sshr v22.8h, v22.8h,#5
Dihevc_intra_pred_chroma_mode_3_to_9.s157 sshr v22.8h, v22.8h,#5
297 sshr v25.8h, v25.8h,#5
419 sshr v14.8h, v14.8h,#5
Dihevc_intra_pred_filters_chroma_mode_11_to_17.s276 sshr v22.8h, v22.8h,#5
419 sshr v12.8h, v12.8h,#5
548 sshr v14.8h, v14.8h,#5
Dihevc_deblk_luma_vert.s531 sshr v16.8h,v16.8h,#1
589 sshr v2.8h,v2.8h,#1
Dihevc_deblk_luma_horz.s518 sshr v0.8b,v0.8b,#1
/external/libavc/common/armv8/
Dih264_iquant_itrans_recon_av8.s169 sshr v8.4h, v1.4h, #1 // d1>>1
170 sshr v9.4h, v3.4h, #1 // d3>>1
200 sshr v18.4h, v11.4h, #1 // q0>>1
201 sshr v19.4h, v13.4h, #1 // q1>>1
357 sshr v8.4h, v1.4h, #1 // d1>>1
358 sshr v9.4h, v3.4h, #1 // d3>>1
389 sshr v18.4h, v11.4h, #1 // q0>>1
390 sshr v19.4h, v13.4h, #1 // q1>>1
641 sshr v16.8h, v9.8h, #1 //(pi2_tmp_ptr[1] >> 1)
642 sshr v17.8h, v10.8h, #1 //(pi2_tmp_ptr[2] >> 1)
[all …]
/external/llvm/test/MC/AArch64/
Dneon-simd-shift.s8 sshr v0.8b, v1.8b, #3
9 sshr v0.4h, v1.4h, #3
10 sshr v0.2s, v1.2s, #3
11 sshr v0.16b, v1.16b, #3
12 sshr v0.8h, v1.8h, #3
13 sshr v0.4s, v1.4s, #3
14 sshr v0.2d, v1.2d, #3
Dneon-scalar-shift-imm.s8 sshr d15, d16, #12
Darm64-advsimd.s1226 sshr d0, d0, #1 define
1275 ; CHECK: sshr d0, d0, #1 ; encoding: [0x00,0x04,0x7f,0x5f]
1400 sshr.8b v0, v0, #1
1401 sshr.16b v0, v0, #2
1402 sshr.4h v0, v0, #3
1403 sshr.8h v0, v0, #4
1404 sshr.2s v0, v0, #5
1405 sshr.4s v0, v0, #6
1406 sshr.2d v0, v0, #7
1407 sshr.8b v0, v0, #1
[all …]
Dneon-diagnostics.s1378 sshr v0.8b, v1.8h, #3
1379 sshr v0.4h, v1.4s, #3
1380 sshr v0.2s, v1.2d, #3
1381 sshr v0.16b, v1.16b, #9
1382 sshr v0.8h, v1.8h, #17
1383 sshr v0.4s, v1.4s, #33
1384 sshr v0.2d, v1.2d, #65
4907 sshr d15, d16, #99
4913 sshr d15, s16, #31
/external/llvm/test/CodeGen/AArch64/
Dcomplex-int-to-fp.ll34 ; CHECK: sshr.2s [[VAL32:v[0-9]+]], [[TMP]], #16
55 ; CHECK: sshr.2s [[VAL32:v[0-9]+]], [[TMP]], #24
93 ; CHECK: sshr.2s [[VAL32:v[0-9]+]], [[TMP]], #16
112 ; CHECK: sshr.2s [[VAL32:v[0-9]+]], [[TMP]], #24
149 ; CHECK: sshr.4h [[VAL16:v[0-9]+]], [[TMP]], #8
Darm64-vselect.ll9 ; sshr.4s v0, v0, #31
Darm64-neon-simd-shift.ll5 ; CHECK: sshr {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, #3
12 ; CHECK: sshr {{v[0-9]+}}.4h, {{v[0-9]+}}.4h, #3
19 ; CHECK: sshr {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, #3
26 ; CHECK: sshr {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, #3
33 ; CHECK: sshr {{v[0-9]+}}.8h, {{v[0-9]+}}.8h, #3
40 ; CHECK: sshr {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, #3
47 ; CHECK: sshr {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, #3
Darm64-vshr.ll51 ; CHECK: sshr d0, d0, #63
Dfp16-v4-instructions.ll137 ; CHECK-NEXT: sshr [[OP2:v[0-9]+\.4h]], [[OP1]], #8
/external/valgrind/none/tests/arm64/
Dfp_and_simd.c4133 GEN_SHIFT_TEST(sshr, 2d, 2d, 1)
4134 GEN_SHIFT_TEST(sshr, 2d, 2d, 13)
4135 GEN_SHIFT_TEST(sshr, 2d, 2d, 64)
4136 GEN_SHIFT_TEST(sshr, 4s, 4s, 1)
4137 GEN_SHIFT_TEST(sshr, 4s, 4s, 13)
4138 GEN_SHIFT_TEST(sshr, 4s, 4s, 32)
4139 GEN_SHIFT_TEST(sshr, 2s, 2s, 1)
4140 GEN_SHIFT_TEST(sshr, 2s, 2s, 13)
4141 GEN_SHIFT_TEST(sshr, 2s, 2s, 32)
4142 GEN_SHIFT_TEST(sshr, 8h, 8h, 1)
[all …]
/external/vixl/src/vixl/a64/
Dlogic-a64.cc1763 LogicVRegister Simulator::sshr(VectorFormat vform, in sshr() function in vixl::Simulator
1779 LogicVRegister shifted_reg = sshr(vform, temp, src, shift); in ssra()
1799 LogicVRegister shifted_reg = sshr(vform, temp, src, shift).Round(vform); in srsra()
2692 LogicVRegister shifted_src = sshr(vformsrc, temp, src, shift); in sqshrn()
2704 LogicVRegister shifted_src = sshr(vformsrc, temp, src, shift); in sqshrn2()
2716 LogicVRegister shifted_src = sshr(vformsrc, temp, src, shift).Round(vformsrc); in sqrshrn()
2728 LogicVRegister shifted_src = sshr(vformsrc, temp, src, shift).Round(vformsrc); in sqrshrn2()
2740 LogicVRegister shifted_src = sshr(vformsrc, temp, src, shift); in sqshrun()
2752 LogicVRegister shifted_src = sshr(vformsrc, temp, src, shift); in sqshrun2()
2764 LogicVRegister shifted_src = sshr(vformsrc, temp, src, shift).Round(vformsrc); in sqrshrun()
[all …]
/external/llvm/test/MC/Disassembler/AArch64/
Darm64-advsimd.txt1832 # CHECK: sshr d0, d0, #63
2126 # CHECK: sshr.8b v0, v0, #7
2127 # CHECK: sshr.16b v0, v0, #6
2128 # CHECK: sshr.4h v0, v0, #13
2129 # CHECK: sshr.8h v0, v0, #12
2130 # CHECK: sshr.2s v0, v0, #27
2131 # CHECK: sshr.4s v0, v0, #26
2132 # CHECK: sshr.2d v0, v0, #57
2133 # CHECK: sshr.8b v0, v0, #7
Dneon-instructions.txt720 # CHECK: sshr v0.8b, v1.8b, #3
721 # CHECK: sshr v0.4h, v1.4h, #3
722 # CHECK: sshr v0.2s, v1.2s, #3
723 # CHECK: sshr v0.16b, v1.16b, #3
724 # CHECK: sshr v0.8h, v1.8h, #3
725 # CHECK: sshr v0.4s, v1.4s, #3
726 # CHECK: sshr v0.2d, v1.2d, #3
1816 # CHECK: sshr d15, d16, #12
/external/boringssl/linux-aarch64/crypto/modes/
Dghashv8-armx.S19 sshr v17.4s,v17.4s,#31 //broadcast carry bit

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