/external/llvm/test/MC/AArch64/ |
D | arm64-simd-ldst.s | 239 st3.8b {v4, v5, v6}, [x19] 240 st3.16b {v4, v5, v6}, [x19] 241 st3.4h {v4, v5, v6}, [x19] 242 st3.8h {v4, v5, v6}, [x19] 243 st3.2s {v4, v5, v6}, [x19] 244 st3.4s {v4, v5, v6}, [x19] 245 st3.2d {v4, v5, v6}, [x19] 247 st3.8b {v10, v11, v12}, [x9] 248 st3.16b {v14, v15, v16}, [x19] 249 st3.4h {v24, v25, v26}, [x29] [all …]
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D | neon-simd-ldst-multi-elem.s | 172 st3 { v0.16b, v1.16b, v2.16b }, [x0] 173 st3 { v15.8h, v16.8h, v17.8h }, [x15] 174 st3 { v31.4s, v0.4s, v1.4s }, [sp] 175 st3 { v0.2d, v1.2d, v2.2d }, [x0] 176 st3 { v0.8b, v1.8b, v2.8b }, [x0] 177 st3 { v15.4h, v16.4h, v17.4h }, [x15] 178 st3 { v31.2s, v0.2s, v1.2s }, [sp] 187 st3 { v0.16b-v2.16b }, [x0] 188 st3 { v15.8h-v17.8h }, [x15] 189 st3 { v31.4s-v1.4s }, [sp] [all …]
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D | neon-simd-ldst-one-elem.s | 148 st3 { v0.b, v1.b, v2.b }[9], [x0] 149 st3 { v15.h, v16.h, v17.h }[7], [x15] 150 st3 { v31.s, v0.s, v1.s }[3], [sp] 151 st3 { v0.d, v1.d, v2.d }[1], [x0] 309 st3 { v0.b, v1.b, v2.b }[9], [x0], #3 310 st3 { v15.h, v16.h, v17.h }[7], [x15], #6 311 st3 { v31.s, v0.s, v1.s }[3], [sp], x3 312 st3 { v0.d, v1.d, v2.d }[1], [x0], x6
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D | neon-simd-post-ldst-multi-elem.s | 343 st3 { v0.16b, v1.16b, v2.16b }, [x0], x1 344 st3 { v15.8h, v16.8h, v17.8h }, [x15], x2 345 st3 { v31.4s, v0.4s, v1.4s }, [sp], #48 346 st3 { v0.2d, v1.2d, v2.2d }, [x0], #48 347 st3 { v0.8b, v1.8b, v2.8b }, [x0], x2 348 st3 { v15.4h, v16.4h, v17.4h }, [x15], x3 349 st3 { v31.2s, v0.2s, v1.2s }, [sp], #24
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D | neon-diagnostics.s | 4091 st3 {v15.8h, v16.8h, v17.4h}, [x15] 4092 st3 {v0.8b, v1,8b, v2.8b, v3.8b}, [x0] 4093 st3 {v0.8b, v2.8b, v3.8b}, [x0] 4094 st3 {v15.8h-v17.4h}, [x15] 4095 st3 {v31.4s-v2.4s}, [sp] 4177 st3 {v5.2s, v6.2s, v7.2s}, [x1], #48 4233 st3 {v15.h, v16.h, v17.h}[-1], [x15] 4292 st3 {v15.h, v16.h, v17.h}[0], [x15], #8
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/external/libvpx/libvpx/vp9/common/mips/dspr2/ |
D | vp9_convolve2_avg_horiz_dspr2.c | 282 uint32_t st1, st2, st3; in convolve_bi_avg_horiz_16_dspr2() local 499 [st1] "=&r" (st1), [st2] "=&r" (st2), [st3] "=&r" (st3), in convolve_bi_avg_horiz_16_dspr2() 531 uint32_t st1, st2, st3; in convolve_bi_avg_horiz_64_dspr2() local 750 [st1] "=&r" (st1), [st2] "=&r" (st2), [st3] "=&r" (st3), in convolve_bi_avg_horiz_64_dspr2()
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D | vp9_convolve2_horiz_dspr2.c | 244 uint32_t st1, st2, st3; in convolve_bi_horiz_16_dspr2() local 419 [st1] "=&r" (st1), [st2] "=&r" (st2), [st3] "=&r" (st3), in convolve_bi_horiz_16_dspr2() 451 uint32_t st1, st2, st3; in convolve_bi_horiz_64_dspr2() local 628 [st1] "=&r" (st1), [st2] "=&r" (st2), [st3] "=&r" (st3), in convolve_bi_horiz_64_dspr2()
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D | vp9_convolve2_dspr2.c | 265 uint32_t st1, st2, st3; in convolve_bi_horiz_16_transposed_dspr2() local 463 [st1] "=&r" (st1), [st2] "=&r" (st2), [st3] "=&r" (st3), in convolve_bi_horiz_16_transposed_dspr2() 497 uint32_t st1, st2, st3; in convolve_bi_horiz_64_transposed_dspr2() local 696 [st1] "=&r" (st1), [st2] "=&r" (st2), [st3] "=&r" (st3), in convolve_bi_horiz_64_transposed_dspr2()
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D | vp9_convolve8_horiz_dspr2.c | 314 uint32_t st1, st2, st3; in convolve_horiz_16_dspr2() local 548 [st1] "=&r" (st1), [st2] "=&r" (st2), [st3] "=&r" (st3), in convolve_horiz_16_dspr2() 584 uint32_t st1, st2, st3; in convolve_horiz_64_dspr2() local 820 [st1] "=&r" (st1), [st2] "=&r" (st2), [st3] "=&r" (st3), in convolve_horiz_64_dspr2()
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D | vp9_convolve8_avg_horiz_dspr2.c | 348 uint32_t st1, st2, st3; in convolve_avg_horiz_16_dspr2() local 624 [st1] "=&r" (st1), [st2] "=&r" (st2), [st3] "=&r" (st3), in convolve_avg_horiz_16_dspr2() 659 uint32_t st1, st2, st3; in convolve_avg_horiz_64_dspr2() local 937 [st1] "=&r" (st1), [st2] "=&r" (st2), [st3] "=&r" (st3), in convolve_avg_horiz_64_dspr2()
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D | vp9_convolve8_dspr2.c | 347 uint32_t st1, st2, st3; in convolve_horiz_16_transposed_dspr2() local 600 [st1] "=&r" (st1), [st2] "=&r" (st2), [st3] "=&r" (st3), in convolve_horiz_16_transposed_dspr2() 637 uint32_t st1, st2, st3; in convolve_horiz_64_transposed_dspr2() local 891 [st1] "=&r" (st1), [st2] "=&r" (st2), [st3] "=&r" (st3), in convolve_horiz_64_transposed_dspr2()
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/external/icu/icu4j/main/classes/charset/src/com/ibm/icu/charset/ |
D | CharsetMBCS.java | 518 int i, st3; in writeStage3Roundtrip() local 565 st3 = tableInts[stage2]; in writeStage3Roundtrip() 566 st3 = (int)(char)(st3 * 16 + (c&0xf)); in writeStage3Roundtrip() 572 p = st3*3; in writeStage3Roundtrip() 578 ints[st3] = (int)value; in writeStage3Roundtrip() 582 chars[st3] = (char)value; in writeStage3Roundtrip() 610 int st1, st2, st3, i; in reconstituteData() local 617 st3 = mbcsTable.mbcsIndex.get(stageUTF8Index++); in reconstituteData() 618 if (st3 != 0) { in reconstituteData() 620 st3>>=4; in reconstituteData() [all …]
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/external/compiler-rt/lib/sanitizer_common/tests/ |
D | sanitizer_libc_test.cc | 94 struct stat st1, st2, st3; in TEST() local 97 EXPECT_EQ(0u, internal_fstat(fd, &st3)); in TEST() 98 EXPECT_EQ(fsize, (uptr)st3.st_size); in TEST()
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/external/apache-harmony/sql/src/test/java/org/apache/harmony/sql/tests/javax/sql/ |
D | StatementEventTest.java | 92 StatementEvent st3 = new StatementEvent(pc, null, new SQLException( in testSerializationCompatibility() local 94 SerializationTest.verifyGolden(this, st3, STATEMENTEVENT_COMPARATOR); in testSerializationCompatibility()
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/external/llvm/test/CodeGen/AArch64/ |
D | arm64-st1.ll | 310 ; CHECK: st3.b 317 ; CHECK: st3.h 324 ; CHECK: st3.s 331 ; CHECK: st3.d 384 ; CHECK: st3.8b 385 call void @llvm.aarch64.neon.st3.v8i8.p0i8(<8 x i8> %A, <8 x i8> %B, <8 x i8> %C, i8* %P) 397 declare void @llvm.aarch64.neon.st3.v8i8.p0i8(<8 x i8>, <8 x i8>, <8 x i8>, i8*) nounwind readonly 409 ; CHECK: st3.16b 410 call void @llvm.aarch64.neon.st3.v16i8.p0i8(<16 x i8> %A, <16 x i8> %B, <16 x i8> %C, i8* %P) 422 declare void @llvm.aarch64.neon.st3.v16i8.p0i8(<16 x i8>, <16 x i8>, <16 x i8>, i8*) nounwind reado… [all …]
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D | arm64-copy-tuple.ll | 91 …tail call void @llvm.aarch64.neon.st3.v8i8.p0i8(<8 x i8> %vec0, <8 x i8> %vec1, <8 x i8> %vec2, i8… 94 …tail call void @llvm.aarch64.neon.st3.v8i8.p0i8(<8 x i8> %vec0, <8 x i8> %vec1, <8 x i8> %vec2, i8… 110 …tail call void @llvm.aarch64.neon.st3.v16i8.p0i8(<16 x i8> %vec0, <16 x i8> %vec1, <16 x i8> %vec2… 113 …tail call void @llvm.aarch64.neon.st3.v16i8.p0i8(<16 x i8> %vec0, <16 x i8> %vec1, <16 x i8> %vec2… 144 declare void @llvm.aarch64.neon.st3.v8i8.p0i8(<8 x i8>, <8 x i8>, <8 x i8>, i8*) 145 declare void @llvm.aarch64.neon.st3.v16i8.p0i8(<16 x i8>, <16 x i8>, <16 x i8>, i8*)
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D | fp16-vector-load-store.ll | 106 declare void @llvm.aarch64.neon.st3.v4f16.p0v4f16(<4 x half>, <4 x half>, <4 x half>, <4 x half>*) 112 declare void @llvm.aarch64.neon.st3.v8f16.p0v8f16(<8 x half>, <8 x half>, <8 x half>, <8 x half>*) 154 ; CHECK: st3 { v0.4h, v1.4h, v2.4h }, [x0] 156 …tail call void @llvm.aarch64.neon.st3.v4f16.p0v4f16(<4 x half> %b, <4 x half> %c, <4 x half> %d, <… 208 ; CHECK: st3 { v0.8h, v1.8h, v2.8h }, [x0] 210 …tail call void @llvm.aarch64.neon.st3.v8f16.p0v8f16(<8 x half> %b, <8 x half> %c, <8 x half> %d, <… 339 ; CHECK: st3 { v0.h, v1.h, v2.h }[2], [x0] 393 ; CHECK: st3 { v0.h, v1.h, v2.h }[2], [x0]
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D | arm64-indexed-vector-ldst.ll | 3856 ;CHECK: st3.16b { v0, v1, v2 }, [x0], #48 3857 call void @llvm.aarch64.neon.st3.v16i8.p0i8(<16 x i8> %B, <16 x i8> %C, <16 x i8> %D, i8* %A) 3864 ;CHECK: st3.16b { v0, v1, v2 }, [x0], x{{[0-9]+}} 3865 call void @llvm.aarch64.neon.st3.v16i8.p0i8(<16 x i8> %B, <16 x i8> %C, <16 x i8> %D, i8* %A) 3870 declare void @llvm.aarch64.neon.st3.v16i8.p0i8(<16 x i8>, <16 x i8>, <16 x i8>, i8*) 3875 ;CHECK: st3.8b { v0, v1, v2 }, [x0], #24 3876 call void @llvm.aarch64.neon.st3.v8i8.p0i8(<8 x i8> %B, <8 x i8> %C, <8 x i8> %D, i8* %A) 3883 ;CHECK: st3.8b { v0, v1, v2 }, [x0], x{{[0-9]+}} 3884 call void @llvm.aarch64.neon.st3.v8i8.p0i8(<8 x i8> %B, <8 x i8> %C, <8 x i8> %D, i8* %A) 3889 declare void @llvm.aarch64.neon.st3.v8i8.p0i8(<8 x i8>, <8 x i8>, <8 x i8>, i8*) [all …]
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/external/icu/icu4c/source/common/ |
D | ucnvmbcs.cpp | 857 uint32_t st3; in ucnv_MBCSGetFilteredUnicodeSetForUnicode() local 897 if((st3=stage2[st2])!=0) { in ucnv_MBCSGetFilteredUnicodeSetForUnicode() 899 stage3=results+st3; in ucnv_MBCSGetFilteredUnicodeSetForUnicode() 943 if((st3=stage2[st2])!=0) { in ucnv_MBCSGetFilteredUnicodeSetForUnicode() 945 stage3=bytes+st3Multiplier*16*(uint32_t)(uint16_t)st3; in ucnv_MBCSGetFilteredUnicodeSetForUnicode() 948 st3>>=16; in ucnv_MBCSGetFilteredUnicodeSetForUnicode() 958 if(st3&1) { in ucnv_MBCSGetFilteredUnicodeSetForUnicode() 978 st3>>=1; in ucnv_MBCSGetFilteredUnicodeSetForUnicode() 984 … if(((st3&1)!=0 || useFallback) && *((const uint16_t *)stage3)>=0x100) { in ucnv_MBCSGetFilteredUnicodeSetForUnicode() 987 st3>>=1; in ucnv_MBCSGetFilteredUnicodeSetForUnicode() [all …]
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D | ucnv_ext.cpp | 1034 int32_t st1, stage1Length, st2, st3, minLength; in ucnv_extGetUnicodeSet() local 1074 if((st3=(int32_t)ps2[st2]<<UCNV_EXT_STAGE_2_LEFT_SHIFT)!=0) { in ucnv_extGetUnicodeSet() 1076 ps3=stage3+st3; in ucnv_extGetUnicodeSet()
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/external/clang/test/CodeGen/ |
D | struct-x86-darwin.c | 15 struct STest3 {char a; short b; int c; } st3; variable
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/external/llvm/test/MC/Disassembler/AArch64/ |
D | arm64-advsimd.txt | 1117 # CHECK: st3.8b { v1, v2, v3 }, [x1] 1118 # CHECK: st3.16b { v5, v6, v7 }, [x2] 1119 # CHECK: st3.2s { v10, v11, v12 }, [x0] 1136 # CHECK: st3.b { v1, v2, v3 }[2], [x3], x4 1137 # CHECK: st3.d { v2, v3, v4 }[1], [x4], x5 1138 # CHECK: st3.h { v3, v4, v5 }[3], [x5], x6 1139 # CHECK: st3.s { v4, v5, v6 }[2], [x6], x7 1146 # CHECK: st3.b { v1, v2, v3 }[2], [x3], #3 1147 # CHECK: st3.d { v2, v3, v4 }[1], [x4], #24 1148 # CHECK: st3.h { v3, v4, v5 }[3], [x5], #6 [all …]
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/external/llvm/test/Transforms/EarlyCSE/AArch64/ |
D | intrinsics.ll | 181 ; Check that @llvm.aarch64.neon.st3 is not optimized away by Early CSE due to 182 ; mismatch between st2 and st3. 184 ; CHECK: call void @llvm.aarch64.neon.st3.v4i32.p0i8 202 call void @llvm.aarch64.neon.st3.v4i32.p0i8(<4 x i32> %4, <4 x i32> %3, <4 x i32> %3, i8* %0) 220 declare void @llvm.aarch64.neon.st3.v4i32.p0i8(<4 x i32>, <4 x i32>, <4 x i32>, i8* nocapture)
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/external/valgrind/none/tests/x86/ |
D | gen_insn_test.pl | 59 st0 => 0, st1 => 1, st2 => 2, st3 => 3,
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/external/valgrind/none/tests/amd64/ |
D | gen_insn_test.pl | 64 st0 => 0, st1 => 1, st2 => 2, st3 => 3,
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