/external/llvm/test/MC/AArch64/ |
D | neon-simd-ldst-multi-elem.s | 205 st4 { v0.16b, v1.16b, v2.16b, v3.16b }, [x0] 206 st4 { v15.8h, v16.8h, v17.8h, v18.8h }, [x15] 207 st4 { v31.4s, v0.4s, v1.4s, v2.4s }, [sp] 208 st4 { v0.2d, v1.2d, v2.2d, v3.2d }, [x0] 209 st4 { v0.8b, v1.8b, v2.8b, v3.8b }, [x0] 210 st4 { v15.4h, v16.4h, v17.4h, v18.4h }, [x15] 211 st4 { v31.2s, v0.2s, v1.2s, v2.2s }, [sp] 220 st4 { v0.16b-v3.16b }, [x0] 221 st4 { v15.8h-v18.8h }, [x15] 222 st4 { v31.4s-v2.4s }, [sp] [all …]
|
D | arm64-simd-ldst.s | 297 st4.8b {v4, v5, v6, v7}, [x19] 298 st4.16b {v4, v5, v6, v7}, [x19] 299 st4.4h {v4, v5, v6, v7}, [x19] 300 st4.8h {v4, v5, v6, v7}, [x19] 301 st4.2s {v4, v5, v6, v7}, [x19] 302 st4.4s {v4, v5, v6, v7}, [x19] 303 st4.2d {v4, v5, v6, v7}, [x19] 314 ; CHECK: st4.8b { v4, v5, v6, v7 }, [x19] ; encoding: [0x64,0x02,0x00,0x0c] 315 ; CHECK: st4.16b { v4, v5, v6, v7 }, [x19] ; encoding: [0x64,0x02,0x00,0x4c] 316 ; CHECK: st4.4h { v4, v5, v6, v7 }, [x19] ; encoding: [0x64,0x06,0x00,0x0c] [all …]
|
D | neon-simd-ldst-one-elem.s | 157 st4 { v0.b, v1.b, v2.b, v3.b }[9], [x0] 158 st4 { v15.h, v16.h, v17.h, v18.h }[7], [x15] 159 st4 { v31.s, v0.s, v1.s, v2.s }[3], [sp] 160 st4 { v0.d, v1.d, v2.d, v3.d }[1], [x0] 318 st4 { v0.b, v1.b, v2.b, v3.b }[9], [x0], x5 319 st4 { v15.h, v16.h, v17.h, v18.h }[7], [x15], x7 320 st4 { v31.s, v0.s, v1.s, v2.s }[3], [sp], #16 321 st4 { v0.d, v1.d, v2.d, v3.d }[1], [x0], #32
|
D | neon-simd-post-ldst-multi-elem.s | 369 st4 { v0.16b, v1.16b, v2.16b, v3.16b }, [x0], x1 370 st4 { v15.8h, v16.8h, v17.8h, v18.8h }, [x15], x2 371 st4 { v31.4s, v0.4s, v1.4s, v2.4s }, [sp], #64 372 st4 { v0.2d, v1.2d, v2.2d, v3.2d }, [x0], #64 373 st4 { v0.8b, v1.8b, v2.8b, v3.8b }, [x0], x3 374 st4 { v15.4h, v16.4h, v17.4h, v18.4h }, [x15], x4 375 st4 { v31.2s, v0.2s, v1.2s, v2.2s }, [sp], #32
|
D | neon-diagnostics.s | 4112 st4 {v15.8h, v16.8h, v17.4h, v18.8h}, [x15] 4113 st4 {v0.8b, v2.8b, v3.8b, v4.8b}, [x0] 4114 st4 {v15.4h, v16.4h, v17.4h, v18.4h, v19.4h}, [x31] 4115 st4 {v15.8h-v18.4h}, [x15] 4116 st4 {v31.2s-v1.2s}, [x31] 4178 st4 {v31.2d, v0.2d, v1.2d, v2.1d}, [x3], x1 4234 st4 {v0.d, v1.d, v2.d, v3.d}[2], [x0] 4293 st4 {v0.b, v1.b, v2.b, v3.b}[1], [x0], #1
|
/external/libavc/common/armv8/ |
D | ih264_deblk_chroma_av8.s | 264 st4 {v0.h, v1.h, v2.h, v3.h}[0], [x12], x1 265 st4 {v0.h, v1.h, v2.h, v3.h}[1], [x12], x1 266 st4 {v0.h, v1.h, v2.h, v3.h}[2], [x12], x1 267 st4 {v0.h, v1.h, v2.h, v3.h}[3], [x12], x1 269 st4 {v4.h, v5.h, v6.h, v7.h}[0], [x12], x1 270 st4 {v4.h, v5.h, v6.h, v7.h}[1], [x12], x1 271 st4 {v4.h, v5.h, v6.h, v7.h}[2], [x12], x1 272 st4 {v4.h, v5.h, v6.h, v7.h}[3], [x12], x1 571 st4 {v0.h, v1.h, v2.h, v3.h}[0], [x12], x1 572 st4 {v0.h, v1.h, v2.h, v3.h}[1], [x12], x1 [all …]
|
/external/llvm/test/CodeGen/AArch64/ |
D | arm64-st1.ll | 343 ; CHECK: st4.b 350 ; CHECK: st4.h 357 ; CHECK: st4.s 364 ; CHECK: st4.d 391 ; CHECK: st4.8b 392 …call void @llvm.aarch64.neon.st4.v8i8.p0i8(<8 x i8> %A, <8 x i8> %B, <8 x i8> %C, <8 x i8> %D, i8*… 398 declare void @llvm.aarch64.neon.st4.v8i8.p0i8(<8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, i8*) nounwind… 416 ; CHECK: st4.16b 417 …call void @llvm.aarch64.neon.st4.v16i8.p0i8(<16 x i8> %A, <16 x i8> %B, <16 x i8> %C, <16 x i8> %D… 423 declare void @llvm.aarch64.neon.st4.v16i8.p0i8(<16 x i8>, <16 x i8>, <16 x i8>, <16 x i8>, i8*) nou… [all …]
|
D | fp16-vector-load-store.ll | 107 declare void @llvm.aarch64.neon.st4.v4f16.p0v4f16(<4 x half>, <4 x half>, <4 x half>, <4 x half>, <… 113 declare void @llvm.aarch64.neon.st4.v8f16.p0v8f16(<8 x half>, <8 x half>, <8 x half>, <8 x half>, <… 163 ; CHECK: st4 { v0.4h, v1.4h, v2.4h, v3.4h }, [x0] 165 …tail call void @llvm.aarch64.neon.st4.v4f16.p0v4f16(<4 x half> %b, <4 x half> %c, <4 x half> %d, <… 217 ; CHECK: st4 { v0.8h, v1.8h, v2.8h, v3.8h }, [x0] 219 …tail call void @llvm.aarch64.neon.st4.v8f16.p0v8f16(<8 x half> %b, <8 x half> %c, <8 x half> %d, <… 348 ; CHECK: st4 { v0.h, v1.h, v2.h, v3.h }[2], [x0] 402 ; CHECK: st4 { v0.h, v1.h, v2.h, v3.h }[2], [x0]
|
D | arm64-indexed-vector-ldst.ll | 4084 ;CHECK: st4.16b { v0, v1, v2, v3 }, [x0], #64 4085 …call void @llvm.aarch64.neon.st4.v16i8.p0i8(<16 x i8> %B, <16 x i8> %C, <16 x i8> %D, <16 x i8> %E… 4092 ;CHECK: st4.16b { v0, v1, v2, v3 }, [x0], x{{[0-9]+}} 4093 …call void @llvm.aarch64.neon.st4.v16i8.p0i8(<16 x i8> %B, <16 x i8> %C, <16 x i8> %D, <16 x i8> %E… 4098 declare void @llvm.aarch64.neon.st4.v16i8.p0i8(<16 x i8>, <16 x i8>, <16 x i8>, <16 x i8>, i8*) 4103 ;CHECK: st4.8b { v0, v1, v2, v3 }, [x0], #32 4104 …call void @llvm.aarch64.neon.st4.v8i8.p0i8(<8 x i8> %B, <8 x i8> %C, <8 x i8> %D, <8 x i8> %E, i8*… 4111 ;CHECK: st4.8b { v0, v1, v2, v3 }, [x0], x{{[0-9]+}} 4112 …call void @llvm.aarch64.neon.st4.v8i8.p0i8(<8 x i8> %B, <8 x i8> %C, <8 x i8> %D, <8 x i8> %E, i8*… 4117 declare void @llvm.aarch64.neon.st4.v8i8.p0i8(<8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, i8*) [all …]
|
D | arm64-copy-tuple.ll | 131 …tail call void @llvm.aarch64.neon.st4.v16i8.p0i8(<16 x i8> %vec0, <16 x i8> %vec1, <16 x i8> %vec2… 134 …tail call void @llvm.aarch64.neon.st4.v16i8.p0i8(<16 x i8> %vec0, <16 x i8> %vec1, <16 x i8> %vec2… 146 declare void @llvm.aarch64.neon.st4.v16i8.p0i8(<16 x i8>, <16 x i8>, <16 x i8>, <16 x i8>, i8*)
|
/external/valgrind/coregrind/m_dispatch/ |
D | dispatch-tilegx-linux.S | 230 st4 r7, r6 277 st4 r7, r6
|
/external/llvm/test/MC/Disassembler/AArch64/ |
D | arm64-advsimd.txt | 1303 # CHECK: st4.8b { v1, v2, v3, v4 }, [x1] 1304 # CHECK: st4.16b { v5, v6, v7, v8 }, [x2] 1305 # CHECK: st4.2s { v10, v11, v12, v13 }, [x0] 1332 # CHECK: st4.b { v1, v2, v3, v4 }[2], [x3], x4 1333 # CHECK: st4.d { v2, v3, v4, v5 }[1], [x4], x5 1334 # CHECK: st4.h { v3, v4, v5, v6 }[3], [x5], x6 1335 # CHECK: st4.s { v4, v5, v6, v7 }[2], [x6], x7 1342 # CHECK: st4.b { v1, v2, v3, v4 }[2], [x3], #4 1343 # CHECK: st4.d { v2, v3, v4, v5 }[1], [x4], #32 1344 # CHECK: st4.h { v3, v4, v5, v6 }[3], [x5], #8 [all …]
|
D | neon-instructions.txt | 2037 # CHECK: st4 { v31.2s, v0.2s, v1.2s, v2.2s }, [sp] 2073 # CHECK: st4 { v31.4s, v0.4s, v1.4s, v2.4s }, [sp], #64 2110 # CHECK: st4 { v0.b, v1.b, v2.b, v3.b }[9], [x0] 2153 # CHECK: st4 { v0.b, v1.b, v2.b, v3.b }[9], [x0], x5
|
/external/valgrind/none/tests/x86/ |
D | gen_insn_test.pl | 60 st4 => 4, st5 => 5, st6 => 6, st7 => 7
|
/external/valgrind/none/tests/amd64/ |
D | gen_insn_test.pl | 65 st4 => 4, st5 => 5, st6 => 6, st7 => 7
|
/external/elfutils/src/tests/ |
D | run-allregs.sh | 76 15: %st4 (st4), float 80 bits 148 37: %st4 (st4), float 80 bits
|
D | run-addrcfi.sh | 47 x87 reg15 (%st4): undefined 94 x87 reg15 (%st4): undefined 168 x87 reg37 (%st4): undefined 234 x87 reg37 (%st4): undefined
|
/external/vixl/src/vixl/a64/ |
D | simulator-a64.h | 1523 void st4(VectorFormat vform, 1529 void st4(VectorFormat vform,
|
D | macro-assembler-a64.h | 2749 st4(vt, vt2, vt3, vt4, dst); in St4() 2776 st4(vt, vt2, vt3, vt4, lane, dst); in St4()
|
D | assembler-a64.h | 3023 void st4(const VRegister& vt, 3030 void st4(const VRegister& vt,
|
D | simulator-a64.cc | 3087 st4(vf, vreg(reg[0]), vreg(reg[1]), vreg(reg[2]), vreg(reg[3]), in NEONLoadStoreMultiStructHelper() 3319 st4(vf, vreg(rt), vreg(rt2), vreg(rt3), vreg(rt4), lane, addr); in NEONLoadStoreSingleStructHelper()
|
D | logic-a64.cc | 662 void Simulator::st4(VectorFormat vform, in st4() function in vixl::Simulator 685 void Simulator::st4(VectorFormat vform, in st4() function in vixl::Simulator
|
/external/vixl/doc/ |
D | supported-instructions.md | 3818 void st4(const VRegister& vt, 3830 void st4(const VRegister& vt,
|
/external/llvm/lib/Target/AArch64/ |
D | AArch64InstrInfo.td | 4746 defm ST4 : SIMDSt4Multiple<"st4">; 4960 defm ST4 : SIMDStSingleB<1, 0b001, "st4", VecListFourb, GPR64pi4>; 4961 defm ST4 : SIMDStSingleH<1, 0b011, 0, "st4", VecListFourh, GPR64pi8>; 4962 defm ST4 : SIMDStSingleS<1, 0b101, 0b00, "st4", VecListFours, GPR64pi16>; 4963 defm ST4 : SIMDStSingleD<1, 0b101, 0b01, "st4", VecListFourd, GPR64pi32>; 4969 defm ST4 : SIMDLdSt4SingleAliases<"st4">;
|
/external/hyphenation-patterns/en-US/ |
D | hyph-en-us.pat.txt | 168 .st4
|