| /external/webrtc/src/modules/audio_coding/codecs/isac/main/source/ |
| D | lattice.c | 37 float sth[MAX_AR_MODEL_ORDER]; in WebRtcIsac_NormLatticeFilterMa() local
52 WebRtcIsac_Dir2Lat(a,orderCoef,sth,cth); in WebRtcIsac_NormLatticeFilterMa()
75 f[i][0] = inv_cth[i-1]*(f[i-1][0] + sth[i-1]*stateG[i-1]); in WebRtcIsac_NormLatticeFilterMa()
76 g[i][0] = cth[i-1]*stateG[i-1] + sth[i-1]* f[i][0]; in WebRtcIsac_NormLatticeFilterMa()
84 f[k+1][n+1] = inv_cth[k]*(f[k][n+1] + sth[k]*g[k][n]); in WebRtcIsac_NormLatticeFilterMa()
85 g[k+1][n+1] = cth[k]*g[k][n] + sth[k]* f[k+1][n+1]; in WebRtcIsac_NormLatticeFilterMa()
118 float sth[MAX_AR_MODEL_ORDER]; in WebRtcIsac_NormLatticeFilterAr() local
132 WebRtcIsac_Dir2Lat(a,orderCoef,sth,cth); in WebRtcIsac_NormLatticeFilterAr()
150 ARf[i][0] = cth[i]*ARf[i+1][0] - sth[i]*stateG[i]; in WebRtcIsac_NormLatticeFilterAr()
151 ARg[i+1][0] = sth[i]*ARf[i+1][0] + cth[i]* stateG[i]; in WebRtcIsac_NormLatticeFilterAr()
[all …]
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| D | codec.h | 213 void WebRtcIsac_Dir2Lat(double* a, int orderCoef, float* sth, float* cth);
|
| /external/llvm/test/MC/Sparc/ |
| D | sparc-mem-instructions.s | 46 ! CHECK: sth %o2, [%i0+%l6] ! encoding: [0xd4,0x36,0x00,0x16]
47 sth %o2, [%i0 + %l6]
48 ! CHECK: sth %o2, [%i0+32] ! encoding: [0xd4,0x36,0x20,0x20]
49 sth %o2, [%i0 + 32]
50 ! CHECK: sth %o2, [%g1] ! encoding: [0xd4,0x30,0x60,0x00]
51 sth %o2, [%g1]
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| /external/llvm/test/CodeGen/BPF/ |
| D | cc_args.ll | 46 ; CHECK: sth 0(r2), r1 # encoding: [0x6b,0x12,0x00,0x00,0x00,0x00,0x00,0x00]
53 ; CHECK: sth 0(r2), r1 # encoding: [0x6b,0x12,0x00,0x00,0x00,0x00,0x00,0x00]
54 ; CHECK: sth 2(r2), r1 # encoding: [0x6b,0x12,0x02,0x00,0x00,0x00,0x00,0x00]
78 ; CHECK: sth 0(r4), r1
82 ; CHECK: sth 0(r4), r3
89 ; CHECK: sth 0(r4), r1
93 ; CHECK: sth 0(r4), r3
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| D | cc_ret.ll | 8 ; CHECK: sth 0(r1), r0
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| /external/llvm/test/CodeGen/SystemZ/ |
| D | int-move-05.ll | 8 ; CHECK: sth %r3, 0(%r2)
17 ; CHECK: sth %r3, 0(%r2)
27 ; CHECK: sth %r3, 0(%r2)
37 ; CHECK: sth %r3, 4094(%r2)
69 ; CHECK: sth %r3, 0(%r2)
101 ; CHECK: sth %r3, 0(%r2)
111 ; CHECK: sth %r4, 4094({{%r3,%r2|%r2,%r3}})
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| D | cond-store-02.ll | 14 ; CHECK: sth %r3, 0(%r2)
30 ; CHECK: sth %r3, 0(%r2)
47 ; CHECK: sth %r3, 0(%r2)
65 ; CHECK: sth %r3, 0(%r2)
84 ; CHECK: sth %r3, 0(%r2)
102 ; CHECK: sth %r3, 0(%r2)
121 ; CHECK: sth %r3, 0(%r2)
139 ; CHECK: sth %r3, 0(%r2)
158 ; CHECK: sth %r3, 0(%r2)
176 ; CHECK: sth %r3, 0(%r2)
[all …]
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| D | atomic-store-02.ll | 7 ; CHECK: sth %r2, 0(%r3)
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| D | unaligned-01.ll | 29 ; CHECK: sth %r2, 0(%r3)
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| D | int-const-04.ll | 105 ; CHECK: sth [[TMP]], 0({{%r2,%r3|%r3,%r2}})
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| D | int-move-08.ll | 83 ; CHECK: sth %r2, 0([[REG]])
|
| /external/llvm/test/CodeGen/PowerPC/ |
| D | jaggedstructs.ll | 28 ; CHECK: sth {{[0-9]+}}, 53(1)
35 ; CHECK: sth {{[0-9]+}}, 70(1)
41 ; CHECK: sth {{[0-9]+}}, 77(1)
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| D | vec_insert.ll | 1 ; RUN: llc < %s -march=ppc32 -mcpu=g5 | grep sth
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| D | structsinregs.ll | 105 ; CHECK: sth 4, 62(1)
143 ; CHECK: sth {{[0-9]+}}, 69(1)
146 ; CHECK: sth {{[0-9]+}}, 94(1)
149 ; CHECK: sth {{[0-9]+}}, 101(1)
192 ; CHECK: sth 4, 62(1)
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| D | unaligned.ll | 14 ; CHECK: sth
18 ; CHECK-VSX: sth
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| D | structsinmem.ll | 63 ; CHECK: sth {{[0-9]+}}, 126(1)
152 ; CHECK: sth {{[0-9]+}}, 126(1)
154 ; CHECK: sth {{[0-9]+}}, 133(1)
158 ; CHECK: sth {{[0-9]+}}, 158(1)
161 ; CHECK: sth {{[0-9]+}}, 165(1)
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| D | pr13891.ll | 9 ; CHECK: sth 3, {{[0-9]+}}(1)
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| D | vec_extload.ll | 33 ; Same as v16si8_sext_in_reg, expands to load/store halfwords (lhz/sth).
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| D | atomics.ll | 55 ; CHECK: sth
|
| /external/llvm/test/MC/Disassembler/Sparc/ |
| D | sparc-mem.txt | 102 # CHECK: sth %o2, [%i0+%l6]
105 # CHECK: sth %o2, [%i0+32]
108 # CHECK: sth %o2, [%g1]
|
| /external/llvm/test/CodeGen/Generic/ |
| D | annotate.ll | 5 @.str = private unnamed_addr constant [4 x i8] c"sth\00", section "llvm.metadata"
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| D | ptr-annotate.ll | 7 @.str = private unnamed_addr constant [4 x i8] c"sth\00", section "llvm.metadata"
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| /external/llvm/test/CodeGen/Hexagon/ |
| D | circ_st.ll | 62 %1 = tail call i8* @llvm.hexagon.circ.sth(i8* %0, i32 0, i32 %or, i32 -2)
68 declare i8* @llvm.hexagon.circ.sth(i8*, i32, i32, i32) nounwind
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| D | brev_st.ll | 66 %1 = tail call i8* @llvm.hexagon.brev.sth(i8* %0, i32 0, i32 %shl)
72 declare i8* @llvm.hexagon.brev.sth(i8*, i32, i32) nounwind
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| /external/llvm/test/CodeGen/SPARC/ |
| D | 64bit.ll | 141 ; CHECK: sth %
176 ; CHECK: sth [[R]], [%i2+40]
|