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/external/libavc/common/armv8/
Dih264_inter_pred_filters_luma_vert_av8.s131 uaddl v12.8h, v4.8b, v6.8b // temp1 = src[2_0] + src[3_0]
136 uaddl v14.8h, v0.8b, v10.8b // temp = src[0_0] + src[5_0]
137 uaddl v16.8h, v2.8b, v8.8b // temp2 = src[1_0] + src[4_0]
139 uaddl v20.8h, v1.8b, v11.8b // temp4 = src[0_8] + src[5_8]
140 uaddl v18.8h, v5.8b, v7.8b // temp3 = src[2_8] + src[3_8]
143 uaddl v26.8h, v3.8b, v9.8b // temp5 = src[1_8] + src[4_8]
144 uaddl v12.8h, v6.8b, v8.8b
146 uaddl v16.8h, v2.8b, v0.8b
147 uaddl v18.8h, v4.8b, v10.8b
150 uaddl v26.8h, v5.8b, v11.8b
[all …]
Dih264_inter_pred_luma_vert_qpel_av8.s138 uaddl v12.8h, v4.8b, v6.8b // temp1 = src[2_0] + src[3_0]
143 uaddl v14.8h, v0.8b, v10.8b // temp = src[0_0] + src[5_0]
144 uaddl v16.8h, v2.8b, v8.8b // temp2 = src[1_0] + src[4_0]
146 uaddl v20.8h, v1.8b, v11.8b // temp4 = src[0_8] + src[5_8]
147 uaddl v18.8h, v5.8b, v7.8b // temp3 = src[2_8] + src[3_8]
150 uaddl v26.8h, v3.8b, v9.8b // temp5 = src[1_8] + src[4_8]
151 uaddl v12.8h, v6.8b, v8.8b
153 uaddl v16.8h, v2.8b, v0.8b
154 uaddl v18.8h, v4.8b, v10.8b
157 uaddl v26.8h, v5.8b, v11.8b
[all …]
Dih264_inter_pred_luma_horz_hpel_vert_hpel_av8.s110 uaddl v20.8h, v4.8b, v6.8b
111 uaddl v18.8h, v0.8b, v10.8b
112 uaddl v22.8h, v2.8b, v8.8b
114 uaddl v24.8h, v5.8b, v7.8b
115 uaddl v20.8h, v1.8b, v11.8b
116 uaddl v26.8h, v3.8b, v9.8b
118 uaddl v24.8h, v14.8b, v15.8b
120 uaddl v22.8h, v12.8b, v17.8b
122 uaddl v26.8h, v13.8b, v16.8b
171 uaddl v24.8h, v7.8b, v9.8b
[all …]
Dih264_inter_pred_luma_horz_hpel_vert_qpel_av8.s160 uaddl v6.8h, v0.8b, v5.8b
164 uaddl v8.8h, v2.8b, v3.8b
168 uaddl v8.8h, v1.8b, v4.8b
172 uaddl v8.8h, v0.8b, v5.8b
175 uaddl v10.8h, v2.8b, v3.8b
182 uaddl v10.8h, v1.8b, v4.8b
186 uaddl v10.8h, v0.8b, v5.8b
189 uaddl v12.8h, v2.8b, v3.8b
196 uaddl v12.8h, v1.8b, v4.8b
200 uaddl v12.8h, v0.8b, v5.8b
[all …]
Dih264_inter_pred_luma_horz_qpel_vert_hpel_av8.s172 uaddl v20.8h, v4.8b, v6.8b
173 uaddl v18.8h, v0.8b, v10.8b
174 uaddl v22.8h, v2.8b, v8.8b
176 uaddl v24.8h, v5.8b, v7.8b
177 uaddl v20.8h, v1.8b, v11.8b
178 uaddl v26.8h, v3.8b, v9.8b
180 uaddl v24.8h, v14.8b, v15.8b
182 uaddl v22.8h, v12.8b, v17.8b
184 uaddl v26.8h, v13.8b, v16.8b
234 uaddl v24.8h, v7.8b, v9.8b
[all …]
Dih264_inter_pred_luma_horz_qpel_vert_qpel_av8.s153 uaddl v24.8h, v0.8b, v10.8b
164 uaddl v28.8h, v18.8b, v23.8b
170 uaddl v24.8h, v1.8b, v11.8b
185 uaddl v24.8h, v18.8b, v23.8b
191 uaddl v16.8h, v2.8b, v12.8b
200 uaddl v24.8h, v3.8b, v13.8b
217 uaddl v28.8h, v18.8b, v23.8b
233 uaddl v24.8h, v18.8b, v23.8b
240 uaddl v16.8h, v4.8b, v14.8b
256 uaddl v24.8h, v5.8b, v15.8b
[all …]
Dih264_intra_pred_luma_8x8_av8.s479 uaddl v20.8h, v0.8b, v2.8b //Adding for FILT121
480 uaddl v22.8h, v1.8b, v3.8b
481 uaddl v24.8h, v2.8b, v4.8b
482 uaddl v26.8h, v3.8b, v5.8b
580 uaddl v20.8h, v0.8b, v2.8b //Adding for FILT121
581 uaddl v22.8h, v1.8b, v3.8b
582 uaddl v24.8h, v2.8b, v4.8b
583 uaddl v26.8h, v3.8b, v5.8b
679 uaddl v20.8h, v0.8b, v2.8b
680 uaddl v22.8h, v1.8b, v3.8b
[all …]
Dih264_inter_pred_filters_luma_horz_av8.s131 uaddl v8.8h, v31.8b, v2.8b //// a0 + a5 (column1,row0)
133 uaddl v10.8h, v30.8b, v3.8b //// a0 + a5 (column2,row0)
135 uaddl v14.8h, v28.8b, v5.8b //// a0 + a5 (column1,row1)
137 uaddl v16.8h, v27.8b, v6.8b //// a0 + a5 (column2,row1)
184 uaddl v8.8h, v31.8b, v2.8b //// a0 + a5 (column1,row2)
186 uaddl v10.8h, v30.8b, v3.8b //// a0 + a5 (column2,row2)
188 uaddl v14.8h, v28.8b, v5.8b //// a0 + a5 (column1,row3)
190 uaddl v16.8h, v27.8b, v6.8b //// a0 + a5 (column2,row3)
236 uaddl v8.8h, v31.8b, v2.8b //// a0 + a5 (column1,row4)
238 uaddl v10.8h, v30.8b, v3.8b //// a0 + a5 (column2,row4)
[all …]
Dih264_inter_pred_luma_horz_qpel_av8.s139 uaddl v8.8h, v31.8b, v2.8b //// a0 + a5 (column1,row0)
141 uaddl v10.8h, v30.8b, v3.8b //// a0 + a5 (column2,row0)
143 uaddl v14.8h, v28.8b, v5.8b //// a0 + a5 (column1,row1)
145 uaddl v16.8h, v27.8b, v6.8b //// a0 + a5 (column2,row1)
200 uaddl v8.8h, v31.8b, v2.8b //// a0 + a5 (column1,row2)
202 uaddl v10.8h, v30.8b, v3.8b //// a0 + a5 (column2,row2)
204 uaddl v14.8h, v28.8b, v5.8b //// a0 + a5 (column1,row3)
206 uaddl v16.8h, v27.8b, v6.8b //// a0 + a5 (column2,row3)
259 uaddl v8.8h, v31.8b, v2.8b //// a0 + a5 (column1,row4)
261 uaddl v10.8h, v30.8b, v3.8b //// a0 + a5 (column2,row4)
[all …]
Dih264_intra_pred_luma_4x4_av8.s424 uaddl v20.8h, v0.8b, v1.8b
425 uaddl v22.8h, v1.8b, v2.8b
508 uaddl v20.8h, v0.8b, v1.8b
509 uaddl v22.8h, v1.8b, v2.8b
591 uaddl v20.8h, v0.8b, v1.8b
592 uaddl v22.8h, v1.8b, v2.8b
675 uaddl v20.8h, v0.8b, v1.8b
676 uaddl v22.8h, v1.8b, v2.8b
762 uaddl v20.8h, v0.8b, v1.8b
763 uaddl v22.8h, v1.8b, v2.8b
[all …]
Dih264_deblk_luma_av8.s155 uaddl v28.8h, v17.8b, v11.8b //
156 uaddl v10.8h, v16.8b, v10.8b //Q14,Q5 = p2 + (p0+q0+1)>>1
157 uaddl v30.8h, v17.8b, v5.8b //
160 uaddl v4.8h, v16.8b, v4.8b //Q15,Q2 = q2 + (p0+q0+1)>>1
276 uaddl v24.8h, v4.8b, v6.8b //p0+q0 L
277 uaddl v26.8h, v5.8b, v7.8b //p0+q0 H
295 uaddl v16.8h, v8.8b, v8.8b //2*q1 L
296 uaddl v0.8h, v9.8b, v9.8b //2*q1 H
317 uaddl v16.8h, v14.8b, v0.8b //q2+q3,L
318 uaddl v0.8h, v15.8b, v1.8b //q2+q3,H
[all …]
Dih264_deblk_chroma_av8.s100 uaddl v8.8h, v6.8b, v0.8b //
101 uaddl v10.8h, v7.8b, v1.8b //Q4,Q5 = q0 + p1
113 uaddl v14.8h, v4.8b, v2.8b //
114 uaddl v28.8h, v5.8b, v3.8b //Q14,Q7 = P0 + Q1
227 uaddl v14.8h, v2.8b, v6.8b
228 uaddl v16.8h, v3.8b, v7.8b //(p0 + q1)
234 uaddl v18.8h, v0.8b, v4.8b
235 uaddl v20.8h, v1.8b, v5.8b //(p1 + q0)
Dih264_intra_pred_luma_16x16_av8.s323 uaddl v2.8h, v0.8b, v1.8b
/external/libavc/encoder/armv8/
Dih264e_half_pel_av8.s108 uaddl v8.8h, v31.8b, v2.8b //// a0 + a5 (column1,row0)
110 uaddl v10.8h, v30.8b, v3.8b //// a0 + a5 (column2,row0)
112 uaddl v12.8h, v29.8b, v4.8b //// a0 + a5 (column3,row0)
114 uaddl v14.8h, v28.8b, v5.8b //// a0 + a5 (column1,row1)
117 uaddl v16.8h, v27.8b, v6.8b //// a0 + a5 (column2,row1)
119 uaddl v18.8h, v26.8b, v7.8b //// a0 + a5 (column3,row1)
303 uaddl v20.8h, v2.8b, v17.8b //// a0 + a5 (column1,row0)
311 uaddl v22.8h, v3.8b, v18.8b //// a0 + a5 (column2,row0)
320 uaddl v24.8h, v4.8b, v19.8b //// a0 + a5 (column3,row0)
410 uaddl v20.8h, v5.8b, v2.8b //// a0 + a5 (column1,row0)
[all …]
Dih264e_evaluate_intra16x16_modes_av8.s129 uaddl v2.8h, v0.8b, v1.8b
/external/libmpeg2/common/armv8/
Dimpeg2_inter_pred.s494 uaddl v0.8h, v0.8b, v1.8b //operate row1
496 uaddl v2.8h, v2.8b, v3.8b //operate row5
498 uaddl v4.8h, v4.8b, v5.8b //operate row2
500 uaddl v6.8h, v6.8b, v7.8b //operate row6
502 uaddl v8.8h, v8.8b, v9.8b //operate row3
504 uaddl v10.8h, v10.8b, v11.8b //operate row7
506 uaddl v12.8h, v12.8b, v13.8b //operate row4
508 uaddl v14.8h, v14.8b, v15.8b //operate row8
510 uaddl v16.8h, v16.8b, v17.8b //operate row9
/external/libhevc/common/arm64/
Dihevc_deblk_luma_horz.s210 uaddl v6.8h, v25.8b , v26.8b
222 uaddl v10.8h, v24.8b , v28.8b
257 uaddl v16.8h, v29.8b , v28.8b
285 uaddl v6.8h, v25.8b , v24.8b
299 uaddl v10.8h, v23.8b , v27.8b
401 uaddl v7.8h, v23.8b , v22.8b
527 uaddl v14.8h, v23.8b , v25.8b
560 uaddl v14.8h, v26.8b , v28.8b
Dihevc_deblk_luma_vert.s207 uaddl v0.8h,v5.8b,v4.8b
232 uaddl v20.8h,v7.8b,v3.8b
275 uaddl v0.8h,v2.8b,v3.8b
284 uaddl v26.8h,v5.8b,v6.8b
520 uaddl v16.8h,v6.8b,v2.8b
582 uaddl v2.8h,v2.8b,v4.8b
/external/llvm/test/MC/AArch64/
Dneon-3vdiff.s33 uaddl v0.8h, v1.8b, v2.8b
34 uaddl v0.4s, v1.4h, v2.4h
35 uaddl v0.2d, v1.2s, v2.2s
Darm64-advsimd.s1913 ; uaddl verbose mode aliases
1914 uaddl v9.8h, v13.8b, v14.8b
1916 uaddl v9.4s, v13.4h, v14.4h
1918 uaddl v9.2d, v13.2s, v14.2s
1920 ; CHECK: uaddl.8h v9, v13, v14 ; encoding: [0xa9,0x01,0x2e,0x2e]
1922 ; CHECK: uaddl.4s v9, v13, v14 ; encoding: [0xa9,0x01,0x6e,0x2e]
1924 ; CHECK: uaddl.2d v9, v13, v14 ; encoding: [0xa9,0x01,0xae,0x2e]
Dneon-diagnostics.s2127 uaddl v0.8h, v1.8h, v2.8b
2128 uaddl v0.4s, v1.4s, v2.4h
2129 uaddl v0.2d, v1.2d, v2.2s
/external/llvm/test/CodeGen/AArch64/
Darm64-vadd.ll209 ;CHECK: uaddl.8h
220 ;CHECK: uaddl.4s
231 ;CHECK: uaddl.2d
Darm64-neon-3vdiff.ll85 ; CHECK: uaddl {{v[0-9]+}}.8h, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
95 ; CHECK: uaddl {{v[0-9]+}}.4s, {{v[0-9]+}}.4h, {{v[0-9]+}}.4h
105 ; CHECK: uaddl {{v[0-9]+}}.2d, {{v[0-9]+}}.2s, {{v[0-9]+}}.2s
/external/llvm/test/MC/Disassembler/AArch64/
Dneon-instructions.txt1139 # CHECK: uaddl v0.8h, v1.8b, v2.8b
1140 # CHECK: uaddl v0.4s, v1.4h, v2.4h
1141 # CHECK: uaddl v0.2d, v1.2s, v2.2s
/external/vixl/src/vixl/a64/
Dsimulator-a64.h1943 LogicVRegister uaddl(VectorFormat vform,

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