| /external/libhevc/common/arm64/ |
| D | ihevc_intra_pred_chroma_dc.s | 134 uaddlp v2.4h, v30.8b
139 uaddlp v3.4h, v31.8b
140 uaddlp v2.2s, v2.4h
141 uaddlp v3.2s, v3.4h
147 uaddlp v2.4h, v26.8b
148 uaddlp v3.4h, v27.8b
150 uaddlp v2.2s, v2.4h
151 uaddlp v3.2s, v3.4h
160 uaddlp v28.4h, v30.8b
161 uaddlp v3.4h, v31.8b
[all …]
|
| D | ihevc_intra_pred_luma_dc.s | 157 uaddlp v2.4h, v0.8b
161 uaddlp v3.4h, v1.8b
169 uaddlp v5.2s, v4.4h
178 uaddlp v2.4h, v0.8b
180 uaddlp v3.4h, v1.8b
187 uaddlp v5.2s, v4.4h
430 uaddlp v2.4h, v0.8b
434 uaddlp v3.4h, v1.8b
439 uaddlp v5.2s, v4.4h
|
| /external/libavc/encoder/armv8/ |
| D | ime_distortion_metrics_av8.s | 133 uaddlp v30.4s, v30.8h
214 uaddlp v30.4s, v30.8h
308 uaddlp v31.4s, v31.8h
357 uaddlp v31.4s, v31.8h
435 uaddlp v30.4s, v30.8h
506 uaddlp v30.4s, v30.8h
600 uaddlp v24.4s, v24.8h
601 uaddlp v26.4s, v26.8h
602 uaddlp v28.4s, v28.8h
603 uaddlp v30.4s, v30.8h
[all …]
|
| D | ih264e_evaluate_intra_chroma_modes_av8.s | 343 uaddlp v16.2s, v16.4h
353 uaddlp v26.2s, v26.4h
362 uaddlp v24.2s, v24.4h ///DC
|
| D | ih264e_evaluate_intra16x16_modes_av8.s | 444 uaddlp v16.2s, v16.4h
454 uaddlp v26.2s, v26.4h
463 uaddlp v24.2s, v24.4h ///DC
|
| /external/llvm/test/MC/AArch64/ |
| D | neon-simd-misc.s | 61 uaddlp v3.8h, v21.16b
62 uaddlp v8.4h, v5.8b
63 uaddlp v9.4s, v1.8h
64 uaddlp v0.2s, v1.4h
65 uaddlp v12.2d, v4.4s
66 uaddlp v17.1d, v28.2s
|
| D | neon-diagnostics.s | 5306 uaddlp v3.8h, v21.8h
5307 uaddlp v8.8b, v5.8b
5308 uaddlp v9.8h, v1.4s
5309 uaddlp v0.4s, v1.2d
|
| D | arm64-advsimd.s | 501 uaddlp.4h v0, v0
551 ; CHECK: uaddlp.4h v0, v0 ; encoding: [0x00,0x28,0x20,0x2e]
|
| /external/llvm/test/CodeGen/AArch64/ |
| D | arm64-vadd.ll | 485 ;CHECK: uaddlp.4h
487 %tmp3 = call <4 x i16> @llvm.aarch64.neon.uaddlp.v4i16.v8i8(<8 x i8> %tmp1)
493 ;CHECK: uaddlp.2s
495 %tmp3 = call <2 x i32> @llvm.aarch64.neon.uaddlp.v2i32.v4i16(<4 x i16> %tmp1)
501 ;CHECK: uaddlp.1d
503 %tmp3 = call <1 x i64> @llvm.aarch64.neon.uaddlp.v1i64.v2i32(<2 x i32> %tmp1)
509 ;CHECK: uaddlp.8h
511 %tmp3 = call <8 x i16> @llvm.aarch64.neon.uaddlp.v8i16.v16i8(<16 x i8> %tmp1)
517 ;CHECK: uaddlp.4s
519 %tmp3 = call <4 x i32> @llvm.aarch64.neon.uaddlp.v4i32.v8i16(<8 x i16> %tmp1)
[all …]
|
| D | arm64-vaddlv.ll | 15 ; CHECK: uaddlp.1d v[[REGNUM:[0-9]+]], v[[INREG:[0-9]+]]
|
| D | machine-copy-prop.ll | 61 %vpadal = call <1 x i64> @llvm.aarch64.neon.uaddlp.v1i64.v2i32(<2 x i32> %sext.i)
97 declare <1 x i64> @llvm.aarch64.neon.uaddlp.v1i64.v2i32(<2 x i32>)
|
| /external/libavc/common/armv8/ |
| D | ih264_intra_pred_luma_8x8_av8.s | 336 uaddlp v1.4h, v0.8b
337 uaddlp v3.2s, v1.4h
338 uaddlp v2.1d, v3.2s
359 uaddlp v14.4h, v10.8b
360 uaddlp v13.2s, v14.4h
361 uaddlp v12.1d, v13.2s
|
| /external/llvm/include/llvm/IR/ |
| D | IntrinsicsAArch64.td | 283 // uaddlp, but tblgen's type inference currently can't handle the
|
| /external/vixl/src/vixl/a64/ |
| D | simulator-a64.h | 1791 LogicVRegister uaddlp(VectorFormat vform,
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| D | macro-assembler-a64.h | 2282 V(uaddlp, Uaddlp) \
|
| D | assembler-a64.h | 2828 void uaddlp(const VRegister& vd,
|
| D | simulator-a64.cc | 2517 case NEON_UADDLP: uaddlp(vf_lp, rd, rn); break; in VisitNEON2RegMisc()
|
| D | logic-a64.cc | 2307 LogicVRegister Simulator::uaddlp(VectorFormat vform, in uaddlp() function in vixl::Simulator
|
| D | assembler-a64.cc | 3969 void Assembler::uaddlp(const VRegister& vd, in uaddlp() function in vixl::Assembler
|
| /external/valgrind/none/tests/arm64/ |
| D | fp_and_simd.stdout.exp | 27406 uaddlp v3.1d, v19.2s 4a7542706dc6b1129248f4d86666aa72 73cb244e2d1853f8dfb5ea4886868f97 00000000…
27407 uaddlp v3.2d, v19.4s a12aa025d4942fdf258180833bfe1b15 40471ea1dd395cfa6505073a50b23089 00000001…
27408 uaddlp v3.2s, v19.4h 61c7a47569d1eb21b21f04d22cd86b83 c2e8ecc49e1e51e218f590180c2dcf25 00000000…
27409 uaddlp v3.4s, v19.8h 352c16ab33bf604b26e141ef79daa064 6101e156a76dd72015fc847a8511fa73 00014257…
27410 uaddlp v3.4h, v19.8b 1d56d5229be51c59222c1f729796300e add7fa61646bfbfa3184f179e727d742 00000000…
27411 uaddlp v3.8h, v19.16b 034a97c638f81d50cd6d37f79250c670 d1f48580e70adcb0495c38cb8121b371 01c5010…
|
| /external/vixl/test/ |
| D | test-simulator-a64.cc | 3957 DEFINE_TEST_NEON_2DIFF_LONG(uaddlp, Basic) in DEFINE_TEST_NEON_2DIFF_FP_SCALAR_SD()
|
| /external/vixl/doc/ |
| D | supported-instructions.md | 4074 void uaddlp(const VRegister& vd,
|
| /external/llvm/test/MC/Disassembler/AArch64/ |
| D | arm64-advsimd.txt | 500 # CHECK: uaddlp.4h v0, v0
|
| /external/llvm/lib/Target/AArch64/ |
| D | AArch64InstrInfo.td | 2663 defm UADDLP : SIMDLongTwoVector<1, 0b00010, "uaddlp",
|