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Searched refs:ule (Results 1 – 25 of 205) sorted by relevance

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/external/llvm/lib/IR/
DConstantRange.cpp225 return Lower.ule(V) && V.ult(Upper); in contains()
226 return Lower.ule(V) || V.ult(Upper); in contains()
241 return Lower.ule(Other.getLower()) && Other.getUpper().ule(Upper); in contains()
245 return Other.getUpper().ule(Upper) || in contains()
246 Lower.ule(Other.getLower()); in contains()
248 return Other.getUpper().ule(Upper) && Lower.ule(Other.getLower()); in contains()
285 if (Upper.ule(CR.Lower)) in intersectWith()
307 if (CR.Upper.ule(Lower)) in intersectWith()
315 if (CR.Upper.ule(Lower)) in intersectWith()
335 if (CR.Upper.ule(Lower)) { in intersectWith()
[all …]
/external/llvm/test/CodeGen/Mips/
Dselect.ll280 ; 32: c.ule.s $[[F2]], $[[F3]]
286 ; 32R2: c.ule.s $[[F2]], $[[F3]]
295 ; 64: c.ule.s $f14, $f15
299 ; 64R2: c.ule.s $f14, $f15
317 ; 32: c.ule.s $[[F2]], $[[F3]]
323 ; 32R2: c.ule.s $[[F2]], $[[F3]]
332 ; 64: c.ule.s $f14, $f15
336 ; 64R2: c.ule.s $f14, $f15
428 ; 32: c.ule.d $[[F2]], $[[F3]]
434 ; 32R2: c.ule.d $[[F2]], $[[F3]]
[all …]
Dsetule.ll15 %cmp = icmp ule i32 %0, %1
22 %cmp1 = icmp ule i32 %2, %1
Dfcmp.ll53 ; 32-C-DAG: c.ule.s $f12, $f14
57 ; 64-C-DAG: c.ule.s $f12, $f13
256 ; 32-CMP-DAG: cmp.ule.s $[[T0:f[0-9]+]], $f14, $f12
260 ; 64-CMP-DAG: cmp.ule.s $[[T0:f[0-9]+]], $f13, $f12
298 ; 32-C-DAG: c.ule.s $f12, $f14
302 ; 64-C-DAG: c.ule.s $f12, $f13
305 ; 32-CMP-DAG: cmp.ule.s $[[T0:f[0-9]+]], $f12, $f14
309 ; 64-CMP-DAG: cmp.ule.s $[[T0:f[0-9]+]], $f12, $f13
313 %1 = fcmp ule float %a, %b
414 ; 32-C-DAG: c.ule.d $f12, $f14
[all …]
Dfpbr.ll50 ; 32-GPR: cmp.ule.s $[[FGRCC:f[0-9]+]], $f14, $f12
51 ; 64-GPR: cmp.ule.s $[[FGRCC:f[0-9]+]], $f13, $f12
138 ; 32-GPR: cmp.ule.d $[[FGRCC:f[0-9]+]], $f14, $f12
139 ; 64-GPR: cmp.ule.d $[[FGRCC:f[0-9]+]], $f13, $f12
/external/llvm/test/CodeGen/R600/
Dllvm.amdgpu.kilp.ll8 %0 = icmp ule i32 0, 3
11 %2 = icmp ule i32 3, 0
Dllvm.AMDGPU.kill.ll10 %0 = icmp ule i32 0, 3
13 %2 = icmp ule i32 3, 0
Dunsupported-cc.ll84 %0 = icmp ule i32 %in, 5
97 %0 = fcmp ule float %in, 5.0
109 %0 = fcmp ule float %in, 5.0
/external/llvm/test/CodeGen/AArch64/
Dcond-sel.ll61 ; Note that commuting rhs and lhs in the select changes ugt to ule (i.e. hi to ls).
77 ; Note that commuting rhs and lhs in the select changes ugt to ule (i.e. hi to ls).
101 ; Note that commuting rhs and lhs in the select changes ugt to ule (i.e. hi to ls).
117 ; Note that commuting rhs and lhs in the select changes ugt to ule (i.e. hi to ls).
141 ; Note that commuting rhs and lhs in the select changes ugt to ule (i.e. hi to ls).
157 ; Note that commuting rhs and lhs in the select changes ugt to ule (i.e. hi to ls).
190 %tst2 = icmp ule i64 %lhs64, %rhs64
209 %tst2 = icmp ule i64 %lhs64, %rhs64
/external/llvm/test/ExecutionEngine/OrcMCJIT/
Dtest-setcond-int.ll23 %test4 = icmp ule i8 %ubyte1, %ubyte2 ; <i1> [#uses=0]
29 %test10 = icmp ule i16 %ushort1, %ushort2 ; <i1> [#uses=0]
35 %test16 = icmp ule i32 %uint1, %uint2 ; <i1> [#uses=0]
41 %test22 = icmp ule i64 %ulong1, %ulong2 ; <i1> [#uses=0]
/external/llvm/test/ExecutionEngine/MCJIT/
Dtest-setcond-int.ll23 %test4 = icmp ule i8 %ubyte1, %ubyte2 ; <i1> [#uses=0]
29 %test10 = icmp ule i16 %ushort1, %ushort2 ; <i1> [#uses=0]
35 %test16 = icmp ule i32 %uint1, %uint2 ; <i1> [#uses=0]
41 %test22 = icmp ule i64 %ulong1, %ulong2 ; <i1> [#uses=0]
/external/llvm/test/ExecutionEngine/
Dtest-interp-vec-setcond-int.ll23 %test4 = icmp ule <5 x i8> %ubyte1, %ubyte2
29 %test10 = icmp ule <4 x i16> %ushort1, %ushort2
35 %test16 = icmp ule <3 x i32> %uint1, %uint2
41 %test22 = icmp ule <2 x i64> %ulong1, %ulong2
/external/llvm/test/Transforms/InstCombine/
D2012-03-10-InstCombine.ll18 %cmp2 = icmp ule i8* %d, %f
26 %not.cmp3 = icmp ule i8* %c, %f
D2007-12-10-ConstFoldCompare.ll7 %cond = icmp ule i8* inttoptr (i64 4294967297 to i8*), inttoptr (i64 5 to i8*)
/external/llvm/test/Transforms/ADCE/
D2002-07-17-PHIAssertion.ll21 %cond241 = icmp ule i32 %reg117, %reg128 ; <i1> [#uses=1]
33 %cond247 = icmp ule i32 %reg126, 7 ; <i1> [#uses=1]
/external/llvm/test/Transforms/InstSimplify/
DAndOrXor.ll55 %2 = icmp ule i32 %1, 3
85 %2 = icmp ule i32 %1, 3
136 %cmp3 = icmp ule i32 %b, 2
146 %cmp3 = icmp ule i32 %b, 2
/external/llvm/test/Bitcode/
DmiscInstructions.3.2.ll84 ; CHECK-NEXT: %res6 = icmp ule i32 %x1, %x2
85 %res6 = icmp ule i32 %x1, %x2
126 ; CHECK-NEXT: %res6 = fcmp ule float %x1, %x2
127 %res6 = fcmp ule float %x1, %x2
/external/llvm/lib/Analysis/
DScalarEvolutionAliasAnalysis.cpp139 if (ASizeInt.ule(SE->getUnsignedRange(BA).getUnsignedMin()) && in alias()
153 if (BSizeInt.ule(SE->getUnsignedRange(AB).getUnsignedMin()) && in alias()
/external/llvm/test/MC/Disassembler/Mips/mips32/
Dvalid-xfail-mips32.txt25 0x46 0x32 0xcf 0x37 # CHECK: c.ule.d $fcc7, $f25, $f18
26 0x46 0x1e 0xaf 0x37 # CHECK: c.ule.s $fcc7, $f21, $f30
/external/icu/icu4c/source/data/unit/
Dksh.txt240 dnam{"Dumm Quecksilbersäule"}
241 one{"{0} Dumm Quecksilbersäule"}
242 other{"{0} Dumm Quecksilbersäule"}
243 zero{"{0} Dumm Quecksilbersäule"}
754 dnam{"Dumm Quecksilbersäule"}
/external/llvm/test/CodeGen/X86/
D2012-07-15-BuildVectorPromote.ll5 %cmp = icmp ule <1 x i32> undef, undef
/external/llvm/test/CodeGen/PowerPC/
D2008-02-09-LocalRegAllocAssert.ll6 %tmp2 = icmp ule i64 %tmp, 0 ; <i1> [#uses=1]
/external/llvm/test/MC/Mips/
Dmips-fpu-instructions.s81 # CHECK: c.ule.d $f12, $f14 # encoding: [0x37,0x60,0x2e,0x46]
82 # CHECK: c.ule.s $f6, $f7 # encoding: [0x37,0x30,0x07,0x46]
114 c.ule.d $f12,$f14
115 c.ule.s $f6,$f7
/external/llvm/test/MC/Disassembler/Mips/mips64r2/
Dvalid-xfail-mips64r2.txt25 0x46 0x32 0xcf 0x37 # CHECK: c.ule.d $fcc7, $f25, $f18
26 0x46 0x1e 0xaf 0x37 # CHECK: c.ule.s $fcc7, $f21, $f30
46 0x46 0xc2 0x86 0x37 # CHECK: c.ule.ps $fcc6, $f16, $f2
/external/llvm/test/MC/Disassembler/Mips/mips64r5/
Dvalid-xfail-mips64r5.txt25 0x46 0x32 0xcf 0x37 # CHECK: c.ule.d $fcc7, $f25, $f18
26 0x46 0x1e 0xaf 0x37 # CHECK: c.ule.s $fcc7, $f21, $f30
46 0x46 0xc2 0x86 0x37 # CHECK: c.ule.ps $fcc6, $f16, $f2

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