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Searched refs:ushl (Results 1 – 18 of 18) sorted by relevance

/external/llvm/test/MC/AArch64/
Dneon-shift.s28 ushl v0.8b, v1.8b, v2.8b
29 ushl v0.16b, v1.16b, v2.16b
30 ushl v0.4h, v1.4h, v2.4h
31 ushl v0.8h, v1.8h, v2.8h
32 ushl v0.2s, v1.2s, v2.2s
33 ushl v0.4s, v1.4s, v2.4s
34 ushl v0.2d, v1.2d, v2.2d
Dneon-scalar-shift.s13 ushl d17, d31, d8
Dneon-diagnostics.s916 ushl v1.16b, v25.16b, v6.8h
972 ushl b2, b0, b1
Darm64-advsimd.s370 ushl.8b v0, v0, v0
441 ; CHECK: ushl.8b v0, v0, v0 ; encoding: [0x00,0x44,0x20,0x2e]
/external/libavc/common/armv8/
Dih264_resi_trans_quant_av8.s586 ushl v14.4s, v14.4s, v22.4s
587 ushl v15.4s, v15.4s, v22.4s
588 ushl v16.4s, v16.4s, v22.4s
589 ushl v17.4s, v17.4s, v22.4s
698 ushl v2.4s, v25.4s, v24.4s //>>qbit
699 ushl v3.4s, v26.4s, v24.4s //>>qbit
/external/llvm/test/CodeGen/AArch64/
Darm64-vshr.ll37 ; CHECK-NEXT: ushl.8h [[REG6:v[0-9]+]], [[REG6]], [[REG5]]
/external/vixl/src/vixl/a64/
Dsimulator-a64.cc2699 case NEON_USHL: ushl(vf, rd, rn, rm); break; in VisitNEON3Same()
2710 case NEON_UQSHL: ushl(vf, rd, rn, rm).UnsignedSaturate(vf); break; in VisitNEON3Same()
2712 case NEON_URSHL: ushl(vf, rd, rn, rm).Round(vf); break; in VisitNEON3Same()
2715 ushl(vf, rd, rn, rm).Round(vf).UnsignedSaturate(vf); in VisitNEON3Same()
3575 case NEON_USHL_scalar: ushl(vf, rd, rn, rm); break; in VisitNEONScalar3Same()
3592 ushl(vf, rd, rn, rm).UnsignedSaturate(vf); in VisitNEONScalar3Same()
3598 ushl(vf, rd, rn, rm).Round(vf); in VisitNEONScalar3Same()
3604 ushl(vf, rd, rn, rm).Round(vf).UnsignedSaturate(vf); in VisitNEONScalar3Same()
Dlogic-a64.cc1608 return ushl(vform, dst, src, shiftreg); in shl()
1660 return ushl(vform, dst, extendedreg, shiftreg); in ushll()
1672 return ushl(vform, dst, extendedreg, shiftreg); in ushll2()
1711 return ushl(vform, dst, src, shiftreg).UnsignedSaturate(vform); in uqshl()
1759 return ushl(vform, dst, src, shiftreg); in ushr()
1919 LogicVRegister Simulator::ushl(VectorFormat vform, in ushl() function in vixl::Simulator
Dsimulator-a64.h1835 LogicVRegister ushl(VectorFormat vform,
Dmacro-assembler-a64.h2200 V(ushl, Ushl) \
Dassembler-a64.h2473 void ushl(const VRegister& vd,
Dassembler-a64.cc3180 V(ushl, NEON_USHL, vd.IsVector() || vd.Is1D()) \
/external/llvm/test/MC/Disassembler/AArch64/
Dneon-instructions.txt383 # CHECK: ushl v10.16b, v5.16b, v2.16b
385 # CHECK: ushl v10.8h, v5.8h, v2.8h
387 # CHECK: ushl v10.4s, v5.4s, v2.4s
455 # CHECK: ushl d0, d0, d0
Darm64-advsimd.txt353 # CHECK: ushl.8b v0, v0, v0
/external/vixl/test/
Dtest-simulator-a64.cc3748 DEFINE_TEST_NEON_3SAME(ushl, Basic)
3801 DEFINE_TEST_NEON_3SAME_SCALAR_D(ushl, Basic)
/external/valgrind/none/tests/arm64/
Dfp_and_simd.stdout.exp28424 ushl d29, d28, d27 592897214b8152cb2d36d12886b57c9d b18ffa4384c81c2496352c363b3c1e00 b6df9db6e4…
28432 ushl v29.2d, v28.2d, v27.2d 900b8a2887430b297066fc8d5b7145b4 331dd6b4e2c2cc2da898c2c201b4cb1b 0…
28433 ushl v29.4s, v28.4s, v27.4s be4a20d6cfa4f083d41c2bb5d5221b48 7843cc5c9c7d97859e6f8122b160be14 9…
28434 ushl v29.2s, v28.2s, v27.2s cc47b5bcac4507811d8a98279a7b9082 b3d667baa346d921cfec638aa2c3d790 b…
28435 ushl v29.8h, v28.8h, v27.8h bd98ae4ee4797459cec425d5ee514816 e76a0d42b970b933be224cec18b0b944 6…
28436 ushl v29.4h, v28.4h, v27.4h 96d06f003a945b3d6cdeb7b51577e8b7 18932069a44f58f0f027203e57fc08e4 6…
28437 ushl v29.16b, v28.16b, v27.16b 4be504a22638dc8ce90ec373a37a6924 8838c901b766a90dfb4da4f233fbf2a2…
28438 ushl v29.8b, v28.8b, v27.8b 84f41f60057f683a2cea187f41ff7fb7 172d10087f18669728cac652149ab5a8 c…
/external/vixl/doc/
Dsupported-instructions.md4464 void ushl(const VRegister& vd,
/external/llvm/lib/Target/AArch64/
DAArch64InstrInfo.td2794 defm USHL : SIMDThreeSameVector<1,0b01000,"ushl", int_aarch64_neon_ushl>;
3014 defm USHL : SIMDThreeScalarD< 1, 0b01000, "ushl", int_aarch64_neon_ushl>;