D | logic-a64.cc | 1659 LogicVRegister extendedreg = uxtl(vform, temp2, src); in ushll() 2437 LogicVRegister Simulator::uxtl(VectorFormat vform, in uxtl() function in vixl::Simulator 2786 uxtl(vform, temp1, src1); in uaddl() 2787 uxtl(vform, temp2, src2); in uaddl() 2810 uxtl(vform, temp, src2); in uaddw() 2878 uxtl(vform, temp1, src1); in usubl() 2879 uxtl(vform, temp2, src2); in usubl() 2902 uxtl(vform, temp, src2); in usubw() 2970 uxtl(vform, temp1, src1); in uabal() 2971 uxtl(vform, temp2, src2); in uabal() [all …]
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