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Searched refs:v32i16 (Results 1 – 10 of 10) sorted by relevance

/external/llvm/include/llvm/CodeGen/
DMachineValueType.h78 v32i16 = 31, // 32 x i16 enumerator
241 SimpleTy == MVT::v64i8 || SimpleTy == MVT::v32i16 || in is512BitVector()
302 case v32i16: return i16; in getVectorElementType()
334 case v32i16: return 32; in getVectorNumElements()
440 case v32i16: in getSizeInBits()
549 if (NumElements == 32) return MVT::v32i16; in getVectorVT()
DValueTypes.td54 def v32i16 : ValueType<512, 31>; // 32 x i16 vector value
/external/llvm/lib/Target/X86/
DX86CallingConv.td57 CCIfType<[v64i8, v32i16, v16i32, v8i64, v16f32, v8f64],
138 CCIfType<[v64i8, v32i16, v16i32, v8i64, v16f32, v8f64],
277 CCIfNotVarArg<CCIfType<[v64i8, v32i16, v16i32, v8i64, v16f32, v8f64],
363 CCIfType<[v64i8, v32i16, v16i32, v8i64, v16f32, v8f64],
465 CCIfNotVarArg<CCIfType<[v64i8, v32i16, v16i32, v8i64, v16f32, v8f64],
476 CCIfType<[v64i8, v32i16, v16i32, v8i64, v16f32, v8f64],
523 CCIfType<[v64i8, v32i16, v16i32, v8i64, v16f32, v8f64],
529 v64i8, v32i16, v16i32, v8i64, v16f32, v8f64],
DX86InstrAVX512.td295 def : Pat<(v8f64 (bitconvert (v32i16 VR512:$src))), (v8f64 VR512:$src)>;
300 def : Pat<(v16f32 (bitconvert (v32i16 VR512:$src))), (v16f32 VR512:$src)>;
304 def : Pat<(v8i64 (bitconvert (v32i16 VR512:$src))), (v8i64 VR512:$src)>;
310 def : Pat<(v16i32 (bitconvert (v32i16 VR512:$src))), (v16i32 VR512:$src)>;
313 def : Pat<(v32i16 (bitconvert (v8i64 VR512:$src))), (v32i16 VR512:$src)>;
314 def : Pat<(v32i16 (bitconvert (v16i32 VR512:$src))), (v32i16 VR512:$src)>;
315 def : Pat<(v32i16 (bitconvert (v64i8 VR512:$src))), (v32i16 VR512:$src)>;
316 def : Pat<(v32i16 (bitconvert (v8f64 VR512:$src))), (v32i16 VR512:$src)>;
317 def : Pat<(v32i16 (bitconvert (v16f32 VR512:$src))), (v32i16 VR512:$src)>;
318 def : Pat<(v32i16 (bitconvert (v16f32 VR512:$src))), (v32i16 VR512:$src)>;
[all …]
DX86RegisterInfo.td457 def VR512 : RegisterClass<"X86", [v16f32, v8f64, v64i8, v32i16, v16i32, v8i64], 512,
DX86InstrFragmentsSIMD.td375 def loadv32i16 : PatFrag<(ops node:$ptr), (v32i16 (load node:$ptr))>;
DX86ISelLowering.cpp1422 addRegisterClass(MVT::v32i16, &X86::VR512RegClass); in X86TargetLowering()
1428 setOperationAction(ISD::LOAD, MVT::v32i16, Legal); in X86TargetLowering()
1432 setOperationAction(ISD::ADD, MVT::v32i16, Legal); in X86TargetLowering()
1434 setOperationAction(ISD::SUB, MVT::v32i16, Legal); in X86TargetLowering()
1436 setOperationAction(ISD::MUL, MVT::v32i16, Legal); in X86TargetLowering()
10033 assert(V1.getSimpleValueType() == MVT::v32i16 && "Bad operand type!"); in lowerV32I16VectorShuffle()
10034 assert(V2.getSimpleValueType() == MVT::v32i16 && "Bad operand type!"); in lowerV32I16VectorShuffle()
10041 return splitAndLowerVectorShuffle(DL, MVT::v32i16, V1, V2, Mask, DAG); in lowerV32I16VectorShuffle()
10092 case MVT::v32i16: in lower512BitVectorShuffle()
20645 case MVT::v32i16: in matchIntegerMINMAX()
/external/llvm/lib/IR/
DValueTypes.cpp149 case MVT::v32i16: return "v32i16"; in getEVTString()
217 case MVT::v32i16: return VectorType::get(Type::getInt16Ty(Context), 32); in getTypeForEVT()
/external/llvm/utils/TableGen/
DCodeGenTarget.cpp91 case MVT::v32i16: return "MVT::v32i16"; in getEnumName()
/external/llvm/include/llvm/IR/
DIntrinsics.td171 def llvm_v32i16_ty : LLVMType<v32i16>; // 32 x i16