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Searched refs:v32i8 (Results 1 – 20 of 20) sorted by relevance

/external/clang/test/CodeGen/
Dsystemz-abi-vector.c31 typedef __attribute__((vector_size(32))) char v32i8; typedef
48 v32i8 pass_v32i8(v32i8 arg) { return arg; } in pass_v32i8()
222 v32i8 va_v32i8(__builtin_va_list l) { return __builtin_va_arg(l, v32i8); } in va_v32i8()
/external/llvm/include/llvm/CodeGen/
DMachineValueType.h71 v32i8 = 24, // 32 x i8 enumerator
234 SimpleTy == MVT::v32i8 || SimpleTy == MVT::v16i16 || in is256BitVector()
295 case v32i8: in getVectorElementType()
333 case v32i8: in getVectorNumElements()
433 case v32i8: in getSizeInBits()
540 if (NumElements == 32) return MVT::v32i8; in getVectorVT()
DValueTypes.td47 def v32i8 : ValueType<256, 24>; // 32 x i8 vector value
/external/llvm/test/CodeGen/X86/
Davx2-cmp.ll25 define <32 x i8> @v32i8-cmp(<32 x i8> %i, <32 x i8> %j) nounwind readnone {
53 define <32 x i8> @v32i8-cmpeq(<32 x i8> %i, <32 x i8> %j) nounwind readnone {
Davx-cmp.ll83 define <32 x i8> @v32i8-cmp(<32 x i8> %i, <32 x i8> %j) nounwind readnone {
127 define <32 x i8> @v32i8-cmpeq(<32 x i8> %i, <32 x i8> %j) nounwind readnone {
/external/llvm/lib/Target/X86/
DX86CallingConv.td51 CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
134 CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
271 CCIfNotVarArg<CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
293 CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
317 CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64], CCPassIndirect<i64>>,
359 CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
460 CCIfNotVarArg<CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
472 CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
519 CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
528 v32i8, v16i16, v8i32, v4i64, v8f32, v4f64,
DX86TargetTransformInfo.cpp150 { ISD::SHL, MVT::v32i8, 42 }, // cmpeqb sequence. in getArithmeticInstrCost()
153 { ISD::SRL, MVT::v32i8, 32*10 }, // Scalarized. in getArithmeticInstrCost()
156 { ISD::SRA, MVT::v32i8, 32*10 }, // Scalarized. in getArithmeticInstrCost()
161 { ISD::SDIV, MVT::v32i8, 32*20 }, in getArithmeticInstrCost()
165 { ISD::UDIV, MVT::v32i8, 32*20 }, in getArithmeticInstrCost()
381 {ISD::VECTOR_SHUFFLE, MVT::v32i8, 9} in getShuffleCost()
687 { ISD::SETCC, MVT::v32i8, 4 }, in getCmpSelInstrCost()
694 { ISD::SETCC, MVT::v32i8, 1 }, in getCmpSelInstrCost()
DX86InstrSSE.td354 def : Pat<(v16i8 (extract_subvector (v32i8 VR256:$src), (iPTR 0))),
355 (v16i8 (EXTRACT_SUBREG (v32i8 VR256:$src), sub_xmm))>;
371 (INSERT_SUBREG (v32i8 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
427 def : Pat<(v4f64 (bitconvert (v32i8 VR256:$src))), (v4f64 VR256:$src)>;
431 def : Pat<(v8f32 (bitconvert (v32i8 VR256:$src))), (v8f32 VR256:$src)>;
436 def : Pat<(v4i64 (bitconvert (v32i8 VR256:$src))), (v4i64 VR256:$src)>;
438 def : Pat<(v32i8 (bitconvert (v4f64 VR256:$src))), (v32i8 VR256:$src)>;
439 def : Pat<(v32i8 (bitconvert (v4i64 VR256:$src))), (v32i8 VR256:$src)>;
440 def : Pat<(v32i8 (bitconvert (v8f32 VR256:$src))), (v32i8 VR256:$src)>;
441 def : Pat<(v32i8 (bitconvert (v8i32 VR256:$src))), (v32i8 VR256:$src)>;
[all …]
DX86RegisterInfo.td443 def VR256 : RegisterClass<"X86", [v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
468 def VR256X : RegisterClass<"X86", [v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
DX86ISelLowering.cpp1023 addRegisterClass(MVT::v32i8, &X86::VR256RegClass); in X86TargetLowering()
1077 setOperationAction(ISD::SRL, MVT::v32i8, Custom); in X86TargetLowering()
1080 setOperationAction(ISD::SHL, MVT::v32i8, Custom); in X86TargetLowering()
1083 setOperationAction(ISD::SRA, MVT::v32i8, Custom); in X86TargetLowering()
1085 setOperationAction(ISD::SETCC, MVT::v32i8, Custom); in X86TargetLowering()
1120 setOperationAction(ISD::ADD, MVT::v32i8, Legal); in X86TargetLowering()
1125 setOperationAction(ISD::SUB, MVT::v32i8, Legal); in X86TargetLowering()
1169 setOperationAction(ISD::ADD, MVT::v32i8, Custom); in X86TargetLowering()
1174 setOperationAction(ISD::SUB, MVT::v32i8, Custom); in X86TargetLowering()
1218 setOperationAction(ISD::VSELECT, MVT::v32i8, Legal); in X86TargetLowering()
[all …]
DX86InstrAVX512.td362 def : Pat<(v4f64 (bitconvert (v32i8 VR256X:$src))), (v4f64 VR256X:$src)>;
366 def : Pat<(v8f32 (bitconvert (v32i8 VR256X:$src))), (v8f32 VR256X:$src)>;
371 def : Pat<(v4i64 (bitconvert (v32i8 VR256X:$src))), (v4i64 VR256X:$src)>;
373 def : Pat<(v32i8 (bitconvert (v4f64 VR256X:$src))), (v32i8 VR256X:$src)>;
374 def : Pat<(v32i8 (bitconvert (v4i64 VR256X:$src))), (v32i8 VR256X:$src)>;
375 def : Pat<(v32i8 (bitconvert (v8f32 VR256X:$src))), (v32i8 VR256X:$src)>;
376 def : Pat<(v32i8 (bitconvert (v8i32 VR256X:$src))), (v32i8 VR256X:$src)>;
377 def : Pat<(v32i8 (bitconvert (v16i16 VR256X:$src))), (v32i8 VR256X:$src)>;
378 def : Pat<(v8i32 (bitconvert (v32i8 VR256X:$src))), (v8i32 VR256X:$src)>;
387 def : Pat<(v16i16 (bitconvert (v32i8 VR256X:$src))), (v16i16 VR256X:$src)>;
DX86InstrFragmentsSIMD.td538 def bc_v32i8 : PatFrag<(ops node:$in), (v32i8 (bitconvert node:$in))>;
/external/llvm/lib/IR/
DValueTypes.cpp142 case MVT::v32i8: return "v32i8"; in getEVTString()
210 case MVT::v32i8: return VectorType::get(Type::getInt8Ty(Context), 32); in getTypeForEVT()
/external/llvm/lib/Target/X86/InstPrinter/
DX86InstComments.cpp324 DecodePSLLDQMask(MVT::v32i8, in EmitAnyX86InstComments()
343 DecodePSRLDQMask(MVT::v32i8, in EmitAnyX86InstComments()
368 DecodePALIGNRMask(MVT::v32i8, in EmitAnyX86InstComments()
458 DecodeUNPCKHMask(MVT::v32i8, ShuffleMask); in EmitAnyX86InstComments()
547 DecodeUNPCKLMask(MVT::v32i8, ShuffleMask); in EmitAnyX86InstComments()
/external/llvm/lib/Target/R600/
DSIRegisterInfo.td200 def SReg_256 : RegisterClass<"AMDGPU", [v32i8, v8i32, v8f32], 256, (add SGPR_256)>;
213 def VReg_256 : RegisterClass<"AMDGPU", [v32i8, v8i32, v8f32], 256, (add VGPR_256)>;
DSIInstructions.td2164 defm : SMRD_Pattern <S_LOAD_DWORDX8_IMM, S_LOAD_DWORDX8_SGPR, v32i8>;
2174 defm : SMRD_Pattern_vi <S_LOAD_DWORDX8_IMM, S_LOAD_DWORDX8_SGPR, v32i8>;
2389 (SIsample i32:$addr, v32i8:$rsrc, v4i32:$sampler, imm),
2394 (name vt:$addr, v32i8:$rsrc, v4i32:$sampler, imm),
2399 (name vt:$addr, v32i8:$rsrc, v4i32:$sampler, TEX_RECT),
2404 (name vt:$addr, v32i8:$rsrc, v4i32:$sampler, TEX_ARRAY),
2410 (name vt:$addr, v32i8:$rsrc, v4i32:$sampler, TEX_SHADOW),
2416 (name vt:$addr, v32i8:$rsrc, v4i32:$sampler, TEX_SHADOW_ARRAY),
2469 (name addr_type:$addr, v32i8:$rsrc, imm),
2474 (name addr_type:$addr, v32i8:$rsrc, TEX_ARRAY),
[all …]
DSIISelLowering.cpp44 addRegisterClass(MVT::v32i8, &AMDGPU::SReg_256RegClass); in SITargetLowering()
DSIInstrInfo.td116 SDTypeProfile<1, 4, [SDTCisVT<0, v4f32>, SDTCisVT<2, v32i8>,
/external/llvm/utils/TableGen/
DCodeGenTarget.cpp84 case MVT::v32i8: return "MVT::v32i8"; in getEnumName()
/external/llvm/include/llvm/IR/
DIntrinsics.td163 def llvm_v32i8_ty : LLVMType<v32i8>; // 32 x i8