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Searched refs:v4i32 (Results 1 – 25 of 201) sorted by relevance

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/external/llvm/test/CodeGen/PowerPC/
Dvaddsplat.ll8 %v4i32 = type <4 x i32>
12 define void @test_v4i32_pos_even(%v4i32* %P, %v4i32* %S) {
13 %p = load %v4i32, %v4i32* %P
14 %r = add %v4i32 %p, < i32 18, i32 18, i32 18, i32 18 >
15 store %v4i32 %r, %v4i32* %S
23 define void @test_v4i32_neg_even(%v4i32* %P, %v4i32* %S) {
24 %p = load %v4i32, %v4i32* %P
25 %r = add %v4i32 %p, < i32 -28, i32 -28, i32 -28, i32 -28 >
26 store %v4i32 %r, %v4i32* %S
78 define void @test_v4i32_pos_odd(%v4i32* %P, %v4i32* %S) {
[all …]
/external/llvm/lib/Target/PowerPC/
DPPCInstrAltivec.td353 [(int_ppc_altivec_mtvscr v4i32:$vB)]>;
364 [(set v4i32:$vD, (int_ppc_altivec_lvewx xoaddr:$src))]>;
367 [(set v4i32:$vD, (int_ppc_altivec_lvx xoaddr:$src))]>;
370 [(set v4i32:$vD, (int_ppc_altivec_lvxl xoaddr:$src))]>;
391 [(int_ppc_altivec_stvewx v4i32:$rS, xoaddr:$dst)]>;
394 [(int_ppc_altivec_stvx v4i32:$rS, xoaddr:$dst)]>;
397 [(int_ppc_altivec_stvxl v4i32:$rS, xoaddr:$dst)]>;
421 v4i32, v4i32, v16i8>;
422 def VSEL : VA1a_Int_Ty<42, "vsel", int_ppc_altivec_vsel, v4i32>;
444 [(set v4i32:$vD, (add v4i32:$vA, v4i32:$vB))]>;
[all …]
DPPCInstrVSX.td90 [(set v4i32:$XT, (int_ppc_vsx_lxvw4x xoaddr:$src))]>;
108 [(store v4i32:$XT, xoaddr:$dst)]>;
707 [(set v4i32:$XT, (and v4i32:$XA, v4i32:$XB))]>;
711 [(set v4i32:$XT, (and v4i32:$XA,
712 (vnot_ppc v4i32:$XB)))]>;
717 [(set v4i32:$XT, (vnot_ppc (or v4i32:$XA,
718 v4i32:$XB)))]>;
722 [(set v4i32:$XT, (or v4i32:$XA, v4i32:$XB))]>;
730 [(set v4i32:$XT, (xor v4i32:$XA, v4i32:$XB))]>;
839 def : Pat<(v2f64 (bitconvert v4i32:$A)),
[all …]
/external/llvm/test/Analysis/CostModel/X86/
Dscalarize.ll13 declare %i4 @llvm.bswap.v4i32(%i4)
16 declare %i4 @llvm.ctpop.v4i32(%i4)
24 ; CHECK32: cost of 12 {{.*}}bswap.v4i32
25 ; CHECK64: cost of 12 {{.*}}bswap.v4i32
26 %r2 = call %i4 @llvm.bswap.v4i32(%i4 undef)
31 ; CHECK32: cost of 12 {{.*}}ctpop.v4i32
32 ; CHECK64: cost of 12 {{.*}}ctpop.v4i32
33 %r4 = call %i4 @llvm.ctpop.v4i32(%i4 undef)
/external/llvm/test/Transforms/InstCombine/
D2012-04-23-Neon-Intrinsics.ll5 …%a = tail call <4 x i32> @llvm.arm.neon.vmulls.v4i32(<4 x i16> %x, <4 x i16> zeroinitializer) noun…
13 …%a = tail call <4 x i32> @llvm.arm.neon.vmulls.v4i32(<4 x i16> %x, <4 x i16> <i16 1, i16 1, i16 1,…
22 …%a = tail call <4 x i32> @llvm.arm.neon.vmulls.v4i32(<4 x i16> <i16 3, i16 3, i16 3, i16 3>, <4 x …
30 …%b = tail call <4 x i32> @llvm.arm.neon.vmulls.v4i32(<4 x i16> <i16 -1, i16 -1, i16 -1, i16 -1>, <…
38 …%b = tail call <4 x i32> @llvm.arm.neon.vmullu.v4i32(<4 x i16> <i16 -1, i16 -1, i16 -1, i16 -1>, <…
46 …%a = tail call <4 x i32> @llvm.arm.neon.vmulls.v4i32(<4 x i16> <i16 2, i16 2, i16 2, i16 2>, <4 x …
50 ; CHECK-NEXT: %a = tail call <4 x i32> @llvm.arm.neon.vmulls.v4i32(<4 x i16> <i16 2, i16 2, i16 2, …
56 …%a = tail call <4 x i32> @llvm.arm.neon.vmulls.v4i32(<4 x i16> <i16 3, i16 3, i16 3, i16 3>, <4 x …
64 declare <4 x i32> @llvm.arm.neon.vmulls.v4i32(<4 x i16>, <4 x i16>) nounwind readnone
65 declare <4 x i32> @llvm.arm.neon.vmullu.v4i32(<4 x i16>, <4 x i16>) nounwind readnone
[all …]
/external/clang/test/CodeGen/
Dmips-vector-arg.c9 typedef int v4i32 __attribute__ ((__vector_size__ (16))); typedef
24 extern test_v4i32_2(v4i32, int, v4i32);
25 void test_v4i32(v4i32 a1, int a2, v4i32 a3) { in test_v4i32()
Dmips-vector-return.c9 typedef int v4i32 __attribute__ ((__vector_size__ (16))); typedef
28 v4i32 test_v4i32(int a) { in test_v4i32()
29 return (v4i32){0, a, 0, 0}; in test_v4i32()
Dcompound-literal.c6 typedef int v4i32 __attribute((vector_size(16)));
7 v4i32 *y = &(v4i32){1,2,3,4};
Dmips-varargs.c10 typedef int v4i32 __attribute__ ((__vector_size__ (16))); typedef
192 v4i32 v = va_arg(va, v4i32); in test_v4i32()
Dmips-inline-asm-modifiers.c8 typedef int v4i32 __attribute__((vector_size(16))); typedef
17 v4i32 v4i32_r; in main()
/external/llvm/test/CodeGen/R600/
Dllvm.SI.image.sample.o.ll9 …%r = call <4 x float> @llvm.SI.image.sample.o.v4i32(<4 x i32> undef, <8 x i32> undef, <4 x i32> un…
23 …%r = call <4 x float> @llvm.SI.image.sample.cl.o.v4i32(<4 x i32> undef, <8 x i32> undef, <4 x i32>…
37 …%r = call <4 x float> @llvm.SI.image.sample.d.o.v4i32(<4 x i32> undef, <8 x i32> undef, <4 x i32> …
51 …%r = call <4 x float> @llvm.SI.image.sample.d.cl.o.v4i32(<4 x i32> undef, <8 x i32> undef, <4 x i3…
65 …%r = call <4 x float> @llvm.SI.image.sample.l.o.v4i32(<4 x i32> undef, <8 x i32> undef, <4 x i32> …
79 …%r = call <4 x float> @llvm.SI.image.sample.b.o.v4i32(<4 x i32> undef, <8 x i32> undef, <4 x i32> …
93 …%r = call <4 x float> @llvm.SI.image.sample.b.cl.o.v4i32(<4 x i32> undef, <8 x i32> undef, <4 x i3…
107 …%r = call <4 x float> @llvm.SI.image.sample.lz.o.v4i32(<4 x i32> undef, <8 x i32> undef, <4 x i32>…
121 …%r = call <4 x float> @llvm.SI.image.sample.cd.o.v4i32(<4 x i32> undef, <8 x i32> undef, <4 x i32>…
135 …%r = call <4 x float> @llvm.SI.image.sample.cd.cl.o.v4i32(<4 x i32> undef, <8 x i32> undef, <4 x i…
[all …]
Dllvm.SI.image.sample.ll9 …%r = call <4 x float> @llvm.SI.image.sample.v4i32(<4 x i32> undef, <8 x i32> undef, <4 x i32> unde…
23 …%r = call <4 x float> @llvm.SI.image.sample.cl.v4i32(<4 x i32> undef, <8 x i32> undef, <4 x i32> u…
37 …%r = call <4 x float> @llvm.SI.image.sample.d.v4i32(<4 x i32> undef, <8 x i32> undef, <4 x i32> un…
51 …%r = call <4 x float> @llvm.SI.image.sample.d.cl.v4i32(<4 x i32> undef, <8 x i32> undef, <4 x i32>…
65 …%r = call <4 x float> @llvm.SI.image.sample.l.v4i32(<4 x i32> undef, <8 x i32> undef, <4 x i32> un…
79 …%r = call <4 x float> @llvm.SI.image.sample.b.v4i32(<4 x i32> undef, <8 x i32> undef, <4 x i32> un…
93 …%r = call <4 x float> @llvm.SI.image.sample.b.cl.v4i32(<4 x i32> undef, <8 x i32> undef, <4 x i32>…
107 …%r = call <4 x float> @llvm.SI.image.sample.lz.v4i32(<4 x i32> undef, <8 x i32> undef, <4 x i32> u…
121 …%r = call <4 x float> @llvm.SI.image.sample.cd.v4i32(<4 x i32> undef, <8 x i32> undef, <4 x i32> u…
135 …%r = call <4 x float> @llvm.SI.image.sample.cd.cl.v4i32(<4 x i32> undef, <8 x i32> undef, <4 x i32…
[all …]
Dllvm.SI.gather4.ll21 …%r = call <4 x float> @llvm.SI.gather4.v4i32(<4 x i32> undef, <32 x i8> undef, <16 x i8> undef, i3…
34 …%r = call <4 x float> @llvm.SI.gather4.cl.v4i32(<4 x i32> undef, <32 x i8> undef, <16 x i8> undef,…
47 …%r = call <4 x float> @llvm.SI.gather4.l.v4i32(<4 x i32> undef, <32 x i8> undef, <16 x i8> undef, …
60 …%r = call <4 x float> @llvm.SI.gather4.b.v4i32(<4 x i32> undef, <32 x i8> undef, <16 x i8> undef, …
73 …%r = call <4 x float> @llvm.SI.gather4.b.cl.v4i32(<4 x i32> undef, <32 x i8> undef, <16 x i8> unde…
112 …%r = call <4 x float> @llvm.SI.gather4.lz.v4i32(<4 x i32> undef, <32 x i8> undef, <16 x i8> undef,…
127 …%r = call <4 x float> @llvm.SI.gather4.o.v4i32(<4 x i32> undef, <32 x i8> undef, <16 x i8> undef, …
140 …%r = call <4 x float> @llvm.SI.gather4.cl.o.v4i32(<4 x i32> undef, <32 x i8> undef, <16 x i8> unde…
166 …%r = call <4 x float> @llvm.SI.gather4.l.o.v4i32(<4 x i32> undef, <32 x i8> undef, <16 x i8> undef…
192 …%r = call <4 x float> @llvm.SI.gather4.b.o.v4i32(<4 x i32> undef, <32 x i8> undef, <16 x i8> undef…
[all …]
/external/llvm/test/CodeGen/ARM/
Dvcvt-v8.ll6 %tmp2 = call <4 x i32> @llvm.arm.neon.vcvtas.v4i32.v4f32(<4 x float> %tmp1)
22 %tmp2 = call <4 x i32> @llvm.arm.neon.vcvtns.v4i32.v4f32(<4 x float> %tmp1)
38 %tmp2 = call <4 x i32> @llvm.arm.neon.vcvtps.v4i32.v4f32(<4 x float> %tmp1)
54 %tmp2 = call <4 x i32> @llvm.arm.neon.vcvtms.v4i32.v4f32(<4 x float> %tmp1)
70 %tmp2 = call <4 x i32> @llvm.arm.neon.vcvtau.v4i32.v4f32(<4 x float> %tmp1)
86 %tmp2 = call <4 x i32> @llvm.arm.neon.vcvtnu.v4i32.v4f32(<4 x float> %tmp1)
102 %tmp2 = call <4 x i32> @llvm.arm.neon.vcvtpu.v4i32.v4f32(<4 x float> %tmp1)
118 %tmp2 = call <4 x i32> @llvm.arm.neon.vcvtmu.v4i32.v4f32(<4 x float> %tmp1)
130 declare <4 x i32> @llvm.arm.neon.vcvtas.v4i32.v4f32(<4 x float>) nounwind readnone
132 declare <4 x i32> @llvm.arm.neon.vcvtns.v4i32.v4f32(<4 x float>) nounwind readnone
[all …]
Dvqdmul.ll37 %tmp3 = call <4 x i32> @llvm.arm.neon.vqdmulh.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2)
55 …%1 = tail call <4 x i32> @llvm.arm.neon.vqdmulh.v4i32(<4 x i32> %arg0_int32x4_t, <4 x i32> %0) ; <…
81 declare <4 x i32> @llvm.arm.neon.vqdmulh.v4i32(<4 x i32>, <4 x i32>) nounwind readnone
115 %tmp3 = call <4 x i32> @llvm.arm.neon.vqrdmulh.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2)
133 …%1 = tail call <4 x i32> @llvm.arm.neon.vqrdmulh.v4i32(<4 x i32> %arg0_int32x4_t, <4 x i32> %0) ; …
159 declare <4 x i32> @llvm.arm.neon.vqrdmulh.v4i32(<4 x i32>, <4 x i32>) nounwind readnone
166 %tmp3 = call <4 x i32> @llvm.arm.neon.vqdmull.v4i32(<4 x i16> %tmp1, <4 x i16> %tmp2)
184 …%1 = tail call <4 x i32> @llvm.arm.neon.vqdmull.v4i32(<4 x i16> %arg0_int16x4_t, <4 x i16> %0) ; <…
197 declare <4 x i32> @llvm.arm.neon.vqdmull.v4i32(<4 x i16>, <4 x i16>) nounwind readnone
206 %tmp4 = call <4 x i32> @llvm.arm.neon.vqdmull.v4i32(<4 x i16> %tmp2, <4 x i16> %tmp3)
[all …]
Dneon-v8.1a.ll9 declare <4 x i32> @llvm.arm.neon.vqrdmulh.v4i32(<4 x i32>, <4 x i32>)
14 declare <4 x i32> @llvm.arm.neon.vqadds.v4i32(<4 x i32>, <4 x i32>)
19 declare <4 x i32> @llvm.arm.neon.vqsubs.v4i32(<4 x i32>, <4 x i32>)
47 %prod = call <4 x i32> @llvm.arm.neon.vqrdmulh.v4i32(<4 x i32> %mhs, <4 x i32> %rhs)
48 %retval = call <4 x i32> @llvm.arm.neon.vqadds.v4i32(<4 x i32> %acc, <4 x i32> %prod)
79 %prod = call <4 x i32> @llvm.arm.neon.vqrdmulh.v4i32(<4 x i32> %mhs, <4 x i32> %rhs)
80 %retval = call <4 x i32> @llvm.arm.neon.vqsubs.v4i32(<4 x i32> %acc, <4 x i32> %prod)
122 %prod = tail call <4 x i32> @llvm.arm.neon.vqrdmulh.v4i32(<4 x i32> %x, <4 x i32> %shuffle)
123 %retval = call <4 x i32> @llvm.arm.neon.vqadds.v4i32(<4 x i32> %acc, <4 x i32> %prod)
162 %prod = tail call <4 x i32> @llvm.arm.neon.vqrdmulh.v4i32(<4 x i32> %x, <4 x i32> %shuffle)
[all …]
Dvpadal.ll71 %tmp3 = call <4 x i32> @llvm.arm.neon.vpadals.v4i32.v8i16(<4 x i32> %tmp1, <8 x i16> %tmp2)
80 %tmp3 = call <2 x i64> @llvm.arm.neon.vpadals.v2i64.v4i32(<2 x i64> %tmp1, <4 x i32> %tmp2)
98 %tmp3 = call <4 x i32> @llvm.arm.neon.vpadalu.v4i32.v8i16(<4 x i32> %tmp1, <8 x i16> %tmp2)
107 %tmp3 = call <2 x i64> @llvm.arm.neon.vpadalu.v2i64.v4i32(<2 x i64> %tmp1, <4 x i32> %tmp2)
120 declare <4 x i32> @llvm.arm.neon.vpadals.v4i32.v8i16(<4 x i32>, <8 x i16>) nounwind readnone
121 declare <2 x i64> @llvm.arm.neon.vpadals.v2i64.v4i32(<2 x i64>, <4 x i32>) nounwind readnone
124 declare <4 x i32> @llvm.arm.neon.vpadalu.v4i32.v8i16(<4 x i32>, <8 x i16>) nounwind readnone
125 declare <2 x i64> @llvm.arm.neon.vpadalu.v2i64.v4i32(<2 x i64>, <4 x i32>) nounwind readnone
/external/llvm/test/Transforms/EarlyCSE/AArch64/
Dintrinsics.ll8 ; CHECK-NOT: call { <4 x i32>, <4 x i32> } @llvm.aarch64.neon.ld2.v4i32.p0i8
25 call void @llvm.aarch64.neon.st2.v4i32.p0i8(<4 x i32> %3, <4 x i32> %4, i8* %0)
27 %vld2 = call { <4 x i32>, <4 x i32> } @llvm.aarch64.neon.ld2.v4i32.p0i8(i8* %5)
42 ; CHECK-NOT: call void @llvm.aarch64.neon.st2.v4i32.p0i8(<4 x i32> %3, <4 x i32> %3, i8* %0)
43 ; CHECK: call void @llvm.aarch64.neon.st2.v4i32.p0i8(<4 x i32> %3, <4 x i32> %4, i8* %0)
60 call void @llvm.aarch64.neon.st2.v4i32.p0i8(<4 x i32> %3, <4 x i32> %3, i8* %0)
61 call void @llvm.aarch64.neon.st2.v4i32.p0i8(<4 x i32> %3, <4 x i32> %4, i8* %0)
63 %vld2 = call { <4 x i32>, <4 x i32> } @llvm.aarch64.neon.ld2.v4i32.p0i8(i8* %5)
78 ; CHECK: call { <4 x i32>, <4 x i32> } @llvm.aarch64.neon.ld2.v4i32.p0i8
79 ; CHECK-NOT: call { <4 x i32>, <4 x i32> } @llvm.aarch64.neon.ld2.v4i32.p0i8
[all …]
/external/llvm/lib/Target/X86/
DX86TargetTransformInfo.cpp139 { ISD::SHL, MVT::v4i32, 1 }, in getArithmeticInstrCost()
140 { ISD::SRL, MVT::v4i32, 1 }, in getArithmeticInstrCost()
141 { ISD::SRA, MVT::v4i32, 1 }, in getArithmeticInstrCost()
197 { ISD::SHL, MVT::v4i32, 1 }, // pslld in getArithmeticInstrCost()
202 { ISD::SRL, MVT::v4i32, 1 }, // psrld. in getArithmeticInstrCost()
207 { ISD::SRA, MVT::v4i32, 1 }, // psrad. in getArithmeticInstrCost()
211 { ISD::SDIV, MVT::v4i32, 19 }, // pmuludq sequence in getArithmeticInstrCost()
212 { ISD::UDIV, MVT::v4i32, 15 }, // pmuludq sequence in getArithmeticInstrCost()
218 if (ISD == ISD::SDIV && LT.second == MVT::v4i32 && ST->hasSSE41()) in getArithmeticInstrCost()
230 (VT == MVT::v4i32 && ST->hasSSE41())) in getArithmeticInstrCost()
[all …]
/external/llvm/lib/Target/R600/
DSITypeRewriter.cpp38 Type *v4i32; member in __anon33e15f910111::SITypeRewriter
59 v4i32 = VectorType::get(Type::getInt32Ty(M.getContext()), 4); in doInitialization()
87 PointerType::get(v4i32,PtrTy->getPointerAddressSpace())); in visitLoadInst()
111 Args.push_back(Builder.CreateBitCast(Arg, v4i32)); in visitCallInst()
112 Types.push_back(v4i32); in visitCallInst()
147 if (I.getDestTy() != v4i32) { in visitBitCast()
152 if (Op->getSrcTy() == v4i32) { in visitBitCast()
/external/llvm/test/CodeGen/AArch64/
Darm64-neon-copyPhysReg-tuple.ll10 …%vld = tail call { <4 x i32>, <4 x i32> } @llvm.aarch64.neon.ld2lane.v4i32.p0i32(<4 x i32> <i32 -1…
12 …%vld1 = tail call { <4 x i32>, <4 x i32> } @llvm.aarch64.neon.ld2lane.v4i32.p0i32(<4 x i32> %extra…
24 …%vld = tail call { <4 x i32>, <4 x i32>, <4 x i32> } @llvm.aarch64.neon.ld3lane.v4i32.p0i32(<4 x i…
26 …%vld1 = tail call { <4 x i32>, <4 x i32>, <4 x i32> } @llvm.aarch64.neon.ld3lane.v4i32.p0i32(<4 x …
39 …%vld = tail call { <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32> } @llvm.aarch64.neon.ld4lane.v4i32.p…
41 …%vld1 = tail call { <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32> } @llvm.aarch64.neon.ld4lane.v4i32.…
46 declare { <4 x i32>, <4 x i32> } @llvm.aarch64.neon.ld2lane.v4i32.p0i32(<4 x i32>, <4 x i32>, i64, …
47 declare { <4 x i32>, <4 x i32>, <4 x i32> } @llvm.aarch64.neon.ld3lane.v4i32.p0i32(<4 x i32>, <4 x …
48 declare { <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32> } @llvm.aarch64.neon.ld4lane.v4i32.p0i32(<4 x …
Darm64-AnInfiniteLoopInDAGCombine.ll5 ; (1) Replacing.3 0x2c509f0: v4i32 = any_extend 0x2c4cd08 [ORD=4]
6 ; With: 0x2c4d128: v4i32 = sign_extend 0x2c4cd08 [ORD=4]
8 ; (2) Replacing.2 0x2c4d128: v4i32 = sign_extend 0x2c4cd08 [ORD=4]
9 ; With: 0x2c509f0: v4i32 = any_extend 0x2c4cd08 [ORD=4]
/external/llvm/lib/Target/ARM/
DARMTargetTransformInfo.cpp81 { ISD::SIGN_EXTEND, MVT::v4i32, MVT::v4i16, 0 }, in getCastInstrCost()
82 { ISD::ZERO_EXTEND, MVT::v4i32, MVT::v4i16, 0 }, in getCastInstrCost()
85 { ISD::TRUNCATE, MVT::v4i32, MVT::v4i64, 0 }, in getCastInstrCost()
86 { ISD::TRUNCATE, MVT::v4i16, MVT::v4i32, 1 }, in getCastInstrCost()
105 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i32, 1 }, in getCastInstrCost()
106 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i32, 1 }, in getCastInstrCost()
129 { ISD::FP_TO_SINT, MVT::v4i32, MVT::v4f32, 1 }, in getCastInstrCost()
130 { ISD::FP_TO_UINT, MVT::v4i32, MVT::v4f32, 1 }, in getCastInstrCost()
351 {ISD::VECTOR_SHUFFLE, MVT::v4i32, 2}, in getShuffleCost()
374 {ISD::VECTOR_SHUFFLE, MVT::v4i32, 2}, in getShuffleCost()
[all …]
DARMInstrNEON.td1100 def VLD1LNq32Pseudo : VLD1QLNPseudo<v4i32, load>;
1402 def VLD1DUPq32 : VLD1QDUP<{1,0,1,?}, "32", v4i32, load,
2088 def VST1LNq32Pseudo : VST1QLNPseudo<v4i32, store, extractelt>;
2130 def VST1LNq32Pseudo_UPD : VST1QLNWBPseudo<v4i32, post_store, extractelt>;
3263 def v4i32 : N2V<op24_23, op21_20, 0b10, op17_16, op11_7, 1, op4,
3266 [(set QPR:$Vd, (v4i32 (OpNode (v4i32 QPR:$Vm))))]>;
3270 [(set QPR:$Vd, (v4i32 (OpNode (v4f32 QPR:$Vm))))]> {
3295 def v4i32 : N2VQInt<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
3296 itinQ, OpcodeStr, !strconcat(Dt, "32"),v4i32,v4i32,IntOp>;
3311 v4i16, v4i32, OpNode>;
[all …]
/external/llvm/test/Transforms/SLPVectorizer/AArch64/
Dmismatched-intrinsics.ll7 ; CHECK: call i64 @llvm.arm64.neon.saddlv.i64.v4i32
10 %vaddlvq_s32.i = tail call i64 @llvm.arm64.neon.saddlv.i64.v4i32(<4 x i32> %in1) #2
17 declare i64 @llvm.arm64.neon.saddlv.i64.v4i32(<4 x i32> %in1)

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