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/external/llvm/test/CodeGen/PowerPC/
Dvec_rounding.ll107 declare <8 x float> @llvm.floor.v8f32(<8 x float> %p)
110 %t = call <8 x float> @llvm.floor.v8f32(<8 x float> %p)
126 declare <8 x float> @llvm.ceil.v8f32(<8 x float> %p)
129 %t = call <8 x float> @llvm.ceil.v8f32(<8 x float> %p)
145 declare <8 x float> @llvm.trunc.v8f32(<8 x float> %p)
148 %t = call <8 x float> @llvm.trunc.v8f32(<8 x float> %p)
164 declare <8 x float> @llvm.nearbyint.v8f32(<8 x float> %p)
167 %t = call <8 x float> @llvm.nearbyint.v8f32(<8 x float> %p)
Dvec_fmuladd.ll8 declare <8 x float> @llvm.fmuladd.v8f32(<8 x float> %val, <8 x float>, <8 x float>)
31 %fmuladd = call <8 x float> @llvm.fmuladd.v8f32 (<8 x float> %x, <8 x float> %x, <8 x float> %x)
Dvec_sqrt.ll11 declare <8 x float> @llvm.sqrt.v8f32(<8 x float> %val)
40 %sqrt = call <8 x float> @llvm.sqrt.v8f32 (<8 x float> %x)
Dfminnum.ll12 declare <8 x float> @llvm.minnum.v8f32(<8 x float>, <8 x float>)
84 %z = call <8 x float> @llvm.minnum.v8f32(<8 x float> %x, <8 x float> %y) readnone
Dfmaxnum.ll12 declare <8 x float> @llvm.maxnum.v8f32(<8 x float>, <8 x float>)
84 %z = call <8 x float> @llvm.maxnum.v8f32(<8 x float> %x, <8 x float> %y) readnone
/external/llvm/test/CodeGen/X86/
Dvec_floor.ll35 %t = call <8 x float> @llvm.floor.v8f32(<8 x float> %p)
38 declare <8 x float> @llvm.floor.v8f32(<8 x float> %p)
71 %t = call <8 x float> @llvm.ceil.v8f32(<8 x float> %p)
74 declare <8 x float> @llvm.ceil.v8f32(<8 x float> %p)
107 %t = call <8 x float> @llvm.trunc.v8f32(<8 x float> %p)
110 declare <8 x float> @llvm.trunc.v8f32(<8 x float> %p)
143 %t = call <8 x float> @llvm.rint.v8f32(<8 x float> %p)
146 declare <8 x float> @llvm.rint.v8f32(<8 x float> %p)
179 %t = call <8 x float> @llvm.nearbyint.v8f32(<8 x float> %p)
182 declare <8 x float> @llvm.nearbyint.v8f32(<8 x float> %p)
Dfnabs.ll54 %fabs = tail call <8 x float> @llvm.fabs.v8f32(< 8 x float> %a) #1
65 %fabs = tail call <8 x float> @llvm.fabs.v8f32(<8 x float> %a) #1
72 declare <8 x float> @llvm.fabs.v8f32(<8 x float> %p)
Dvec_fabs.ll35 %t = call <8 x float> @llvm.fabs.v8f32(<8 x float> %p)
38 declare <8 x float> @llvm.fabs.v8f32(<8 x float> %p)
Dsqrt-fastmath.ll9 declare <8 x float> @llvm.sqrt.v8f32(<8 x float>) #0
133 %sqrt = tail call <8 x float> @llvm.sqrt.v8f32(<8 x float> %x)
/external/llvm/lib/Target/X86/
DX86TargetTransformInfo.cpp373 {ISD::VECTOR_SHUFFLE, MVT::v8f32, 1}, // vblendps in getShuffleCost()
497 { ISD::FP_EXTEND, MVT::v8f64, MVT::v8f32, 1 }, in getCastInstrCost()
499 { ISD::FP_ROUND, MVT::v8f32, MVT::v8f64, 1 }, in getCastInstrCost()
567 { ISD::FP_EXTEND, MVT::v8f64, MVT::v8f32, 3 }, in getCastInstrCost()
568 { ISD::FP_ROUND, MVT::v8f32, MVT::v8f64, 3 }, in getCastInstrCost()
570 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i32, 8 }, in getCastInstrCost()
600 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i1, 8 }, in getCastInstrCost()
601 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i8, 8 }, in getCastInstrCost()
602 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i16, 5 }, in getCastInstrCost()
603 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i32, 1 }, in getCastInstrCost()
[all …]
DX86InstrFMA.td90 loadv8f32, X86Fmadd, v4f32, v8f32>;
92 loadv8f32, X86Fmsub, v4f32, v8f32>;
95 v4f32, v8f32>;
98 v4f32, v8f32>;
117 loadv8f32, X86Fnmadd, v4f32, v8f32>;
119 loadv8f32, X86Fnmsub, v4f32, v8f32>;
362 defm VFMADDPS4 : fma4p<0x68, "vfmaddps", X86Fmadd, v4f32, v8f32,
364 defm VFMSUBPS4 : fma4p<0x6C, "vfmsubps", X86Fmsub, v4f32, v8f32,
366 defm VFNMADDPS4 : fma4p<0x78, "vfnmaddps", X86Fnmadd, v4f32, v8f32,
368 defm VFNMSUBPS4 : fma4p<0x7C, "vfnmsubps", X86Fnmsub, v4f32, v8f32,
[all …]
DX86CallingConv.td51 CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
107 CCIfType<[v8f32, v4f64, v8i32, v4i64],
134 CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
271 CCIfNotVarArg<CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
293 CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
317 CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64], CCPassIndirect<i64>>,
359 CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
460 CCIfNotVarArg<CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
472 CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
519 CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
[all …]
DX86InstrSSE.td344 def : Pat<(v4f32 (extract_subvector (v8f32 VR256:$src), (iPTR 0))),
345 (v4f32 (EXTRACT_SUBREG (v8f32 VR256:$src), sub_xmm))>;
367 (INSERT_SUBREG (v8f32 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
377 def : Pat<(v8f32 (scalar_to_vector FR32:$src)),
423 def : Pat<(v4f64 (bitconvert (v8f32 VR256:$src))), (v4f64 VR256:$src)>;
428 def : Pat<(v8f32 (bitconvert (v8i32 VR256:$src))), (v8f32 VR256:$src)>;
429 def : Pat<(v8f32 (bitconvert (v4i64 VR256:$src))), (v8f32 VR256:$src)>;
430 def : Pat<(v8f32 (bitconvert (v4f64 VR256:$src))), (v8f32 VR256:$src)>;
431 def : Pat<(v8f32 (bitconvert (v32i8 VR256:$src))), (v8f32 VR256:$src)>;
432 def : Pat<(v8f32 (bitconvert (v16i16 VR256:$src))), (v8f32 VR256:$src)>;
[all …]
DX86InstrAVX512.td358 def : Pat<(v4f64 (bitconvert (v8f32 VR256X:$src))), (v4f64 VR256X:$src)>;
363 def : Pat<(v8f32 (bitconvert (v8i32 VR256X:$src))), (v8f32 VR256X:$src)>;
364 def : Pat<(v8f32 (bitconvert (v4i64 VR256X:$src))), (v8f32 VR256X:$src)>;
365 def : Pat<(v8f32 (bitconvert (v4f64 VR256X:$src))), (v8f32 VR256X:$src)>;
366 def : Pat<(v8f32 (bitconvert (v32i8 VR256X:$src))), (v8f32 VR256X:$src)>;
367 def : Pat<(v8f32 (bitconvert (v16i16 VR256X:$src))), (v8f32 VR256X:$src)>;
368 def : Pat<(v4i64 (bitconvert (v8f32 VR256X:$src))), (v4i64 VR256X:$src)>;
375 def : Pat<(v32i8 (bitconvert (v8f32 VR256X:$src))), (v32i8 VR256X:$src)>;
380 def : Pat<(v8i32 (bitconvert (v8f32 VR256X:$src))), (v8i32 VR256X:$src)>;
383 def : Pat<(v16i16 (bitconvert (v8f32 VR256X:$src))), (v16i16 VR256X:$src)>;
[all …]
/external/llvm/include/llvm/CodeGen/
DMachineValueType.h99 v8f32 = 48, // 8 x f32 enumerator
233 return (SimpleTy == MVT::v8f32 || SimpleTy == MVT::v4f64 || in is256BitVector()
319 case v8f32: in getVectorElementType()
349 case v8f32: in getVectorNumElements()
437 case v8f32: in getSizeInBits()
574 if (NumElements == 8) return MVT::v8f32; in getVectorVT()
/external/clang/test/CodeGen/
Dx86_64-arguments.c190 typedef float v8f32 __attribute__((__vector_size__(32))); typedef
192 v8f32 v;
201 v8f32 v[1];
/external/llvm/lib/Target/ARM/
DARMTargetTransformInfo.cpp120 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i16, 4 }, in getCastInstrCost()
121 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i16, 4 }, in getCastInstrCost()
122 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i32, 2 }, in getCastInstrCost()
123 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i32, 2 }, in getCastInstrCost()
149 { ISD::FP_TO_SINT, MVT::v8i16, MVT::v8f32, 4 }, in getCastInstrCost()
150 { ISD::FP_TO_UINT, MVT::v8i16, MVT::v8f32, 4 }, in getCastInstrCost()
/external/llvm/test/CodeGen/R600/
Dllvm.round.ll56 %result = call <8 x float> @llvm.round.v8f32(<8 x float> %in) #1
64 declare <8 x float> @llvm.round.v8f32(<8 x float>) #1
Dftrunc.ll9 declare <8 x float> @llvm.trunc.v8f32(<8 x float>) nounwind readnone
78 %y = call <8 x float> @llvm.trunc.v8f32(<8 x float> %x) nounwind readnone
Dfceil.ll9 declare <8 x float> @llvm.ceil.v8f32(<8 x float>) nounwind readnone
86 %y = call <8 x float> @llvm.ceil.v8f32(<8 x float> %x) nounwind readnone
/external/llvm/lib/Target/X86/InstPrinter/
DX86InstComments.cpp171 DecodeBLENDMask(MVT::v8f32, in EmitAnyX86InstComments()
271 DecodeMOVSHDUPMask(MVT::v8f32, ShuffleMask); in EmitAnyX86InstComments()
279 DecodeMOVSLDUPMask(MVT::v8f32, ShuffleMask); in EmitAnyX86InstComments()
663 DecodeSHUFPMask(MVT::v8f32, in EmitAnyX86InstComments()
710 DecodeUNPCKLMask(MVT::v8f32, ShuffleMask); in EmitAnyX86InstComments()
762 DecodeUNPCKHMask(MVT::v8f32, ShuffleMask); in EmitAnyX86InstComments()
789 DecodePSHUFMask(MVT::v8f32, in EmitAnyX86InstComments()
/external/llvm/test/CodeGen/AArch64/
Darm64-fmuladd.ll44 …%tmp4 = call <8 x float> @llvm.fmuladd.v8f32(<8 x float> %tmp1, <8 x float> %tmp2, <8 x float> %tm…
85 declare <8 x float> @llvm.fmuladd.v8f32(<8 x float>, <8 x float>, <8 x float>) nounwind readnone
/external/llvm/test/Analysis/CostModel/X86/
Dmasked-intrinsic-cost.ll32 …%res = call <8 x float> @llvm.masked.load.v8f32(<8 x float>* %addr, i32 4, <8 x i1>%mask, <8 x flo…
80 declare <8 x float> @llvm.masked.load.v8f32(<8 x float>*, i32, <8 x i1>, <8 x float>)
/external/llvm/lib/IR/
DValueTypes.cpp166 case MVT::v8f32: return "v8f32"; in getEVTString()
234 case MVT::v8f32: return VectorType::get(Type::getFloatTy(Context), 8); in getTypeForEVT()
/external/llvm/lib/Target/R600/
DSIRegisterInfo.td200 def SReg_256 : RegisterClass<"AMDGPU", [v32i8, v8i32, v8f32], 256, (add SGPR_256)>;
213 def VReg_256 : RegisterClass<"AMDGPU", [v32i8, v8i32, v8f32], 256, (add VGPR_256)>;

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