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Searched refs:vform (Results 1 – 5 of 5) sorted by relevance

/external/vixl/src/vixl/a64/
Dlogic-a64.cc386 void Simulator::ld1(VectorFormat vform, in ld1() argument
389 dst.ClearForWrite(vform); in ld1()
390 for (int i = 0; i < LaneCountFromFormat(vform); i++) { in ld1()
391 dst.ReadUintFromMem(vform, i, addr); in ld1()
392 addr += LaneSizeInBytesFromFormat(vform); in ld1()
397 void Simulator::ld1(VectorFormat vform, in ld1() argument
401 dst.ReadUintFromMem(vform, index, addr); in ld1()
405 void Simulator::ld1r(VectorFormat vform, in ld1r() argument
408 dst.ClearForWrite(vform); in ld1r()
409 for (int i = 0; i < LaneCountFromFormat(vform); i++) { in ld1r()
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Dinstructions-a64.cc396 VectorFormat VectorFormatHalfWidth(const VectorFormat vform) { in VectorFormatHalfWidth() argument
397 VIXL_ASSERT(vform == kFormat8H || vform == kFormat4S || vform == kFormat2D || in VectorFormatHalfWidth()
398 vform == kFormatH || vform == kFormatS || vform == kFormatD); in VectorFormatHalfWidth()
399 switch (vform) { in VectorFormatHalfWidth()
411 VectorFormat VectorFormatDoubleWidth(const VectorFormat vform) { in VectorFormatDoubleWidth() argument
412 VIXL_ASSERT(vform == kFormat8B || vform == kFormat4H || vform == kFormat2S || in VectorFormatDoubleWidth()
413 vform == kFormatB || vform == kFormatH || vform == kFormatS); in VectorFormatDoubleWidth()
414 switch (vform) { in VectorFormatDoubleWidth()
426 VectorFormat VectorFormatFillQ(const VectorFormat vform) { in VectorFormatFillQ() argument
427 switch (vform) { in VectorFormatFillQ()
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Dsimulator-a64.h460 int64_t Int(VectorFormat vform, int index) const { in Int() argument
462 switch (LaneSizeInBitsFromFormat(vform)) { in Int()
472 uint64_t Uint(VectorFormat vform, int index) const { in Uint() argument
474 switch (LaneSizeInBitsFromFormat(vform)) { in Uint()
484 int64_t IntLeftJustified(VectorFormat vform, int index) const { in IntLeftJustified() argument
485 return Int(vform, index) << (64 - LaneSizeInBitsFromFormat(vform)); in IntLeftJustified()
488 uint64_t UintLeftJustified(VectorFormat vform, int index) const { in UintLeftJustified() argument
489 return Uint(vform, index) << (64 - LaneSizeInBitsFromFormat(vform)); in UintLeftJustified()
492 void SetInt(VectorFormat vform, int index, int64_t value) const { in SetInt() argument
493 switch (LaneSizeInBitsFromFormat(vform)) { in SetInt()
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Dinstructions-a64.h451 VectorFormat VectorFormatHalfWidth(const VectorFormat vform);
452 VectorFormat VectorFormatDoubleWidth(const VectorFormat vform);
453 VectorFormat VectorFormatDoubleLanes(const VectorFormat vform);
454 VectorFormat VectorFormatHalfLanes(const VectorFormat vform);
456 VectorFormat VectorFormatHalfWidthDoubleLanes(const VectorFormat vform);
457 VectorFormat VectorFormatFillQ(const VectorFormat vform);
458 unsigned RegisterSizeInBitsFromFormat(VectorFormat vform);
459 unsigned RegisterSizeInBytesFromFormat(VectorFormat vform);
461 unsigned LaneSizeInBitsFromFormat(VectorFormat vform);
462 int LaneSizeInBytesFromFormat(VectorFormat vform);
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Dsimulator-a64.cc459 VectorFormat vform) { in GetPrintRegisterFormat() argument
460 switch (vform) { in GetPrintRegisterFormat()
2219 VectorFormat vform = (instr->Mask(FP64) == FP64) ? kFormatD : kFormatS; in VisitFPDataProcessing1Source() local
2241 case FSQRT_d: fsqrt(vform, rd, rn); return; in VisitFPDataProcessing1Source()
2260 frint(vform, rd, rn, fpcr_rounding, inexact_exception); in VisitFPDataProcessing1Source()
2267 VectorFormat vform = (instr->Mask(FP64) == FP64) ? kFormatD : kFormatS; in VisitFPDataProcessing2Source() local
2274 case FADD_d: fadd(vform, rd, rn, rm); break; in VisitFPDataProcessing2Source()
2276 case FSUB_d: fsub(vform, rd, rn, rm); break; in VisitFPDataProcessing2Source()
2278 case FMUL_d: fmul(vform, rd, rn, rm); break; in VisitFPDataProcessing2Source()
2280 case FNMUL_d: fnmul(vform, rd, rn, rm); break; in VisitFPDataProcessing2Source()
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