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Searched refs:vtbl (Results 1 – 25 of 91) sorted by relevance

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/external/mesa3d/src/mesa/drivers/dri/i965/
Dbrw_vtbl.c236 brw->intel.vtbl.check_vertex_size = 0; in brwInitVtbl()
237 brw->intel.vtbl.emit_state = 0; in brwInitVtbl()
238 brw->intel.vtbl.reduced_primitive_state = 0; in brwInitVtbl()
239 brw->intel.vtbl.render_start = 0; in brwInitVtbl()
240 brw->intel.vtbl.update_texture_state = 0; in brwInitVtbl()
242 brw->intel.vtbl.invalidate_state = brw_invalidate_state; in brwInitVtbl()
243 brw->intel.vtbl.new_batch = brw_new_batch; in brwInitVtbl()
244 brw->intel.vtbl.finish_batch = brw_finish_batch; in brwInitVtbl()
245 brw->intel.vtbl.destroy = brw_destroy_context; in brwInitVtbl()
246 brw->intel.vtbl.update_draw_buffer = brw_update_draw_buffer; in brwInitVtbl()
[all …]
Dintel_batchbuffer.c155 if (intel->vtbl.debug_batch != NULL) in do_batch_dump()
156 intel->vtbl.debug_batch(intel); in do_batch_dump()
189 if (unlikely(INTEL_DEBUG & DEBUG_AUB) && intel->vtbl.annotate_aub) in do_flush_locked()
190 intel->vtbl.annotate_aub(intel); in do_flush_locked()
208 intel->vtbl.new_batch(intel); in do_flush_locked()
233 if (intel->vtbl.finish_batch) in _intel_batchbuffer_flush()
234 intel->vtbl.finish_batch(intel); in _intel_batchbuffer_flush()
/external/llvm/test/MC/ARM/
Dneon-table-encoding.s3 vtbl.8 d16, {d17}, d16
4 vtbl.8 d16, {d16, d17}, d18
5 vtbl.8 d16, {d16, d17, d18}, d20
6 vtbl.8 d16, {d16, d17, d18, d19}, d20
8 @ CHECK: vtbl.8 d16, {d17}, d16 @ encoding: [0xa0,0x08,0xf1,0xf3]
9 @ CHECK: vtbl.8 d16, {d16, d17}, d18 @ encoding: [0xa2,0x09,0xf0,0xf3]
10 @ CHECK: vtbl.8 d16, {d16, d17, d18}, d20 @ encoding: [0xa4,0x0a,0xf0,0xf3]
11 @ CHECK: vtbl.8 d16, {d16, d17, d18, d19}, d20 @ encoding: [0xa4,0x0b,0xf0,0xf3]
Dneont2-table-encoding.s5 vtbl.8 d16, {d17}, d16
6 vtbl.8 d16, {d16, d17}, d18
7 vtbl.8 d16, {d16, d17, d18}, d20
8 vtbl.8 d16, {d16, d17, d18, d19}, d20
10 @ CHECK: vtbl.8 d16, {d17}, d16 @ encoding: [0xf1,0xff,0xa0,0x08]
11 @ CHECK: vtbl.8 d16, {d16, d17}, d18 @ encoding: [0xf0,0xff,0xa2,0x09]
12 @ CHECK: vtbl.8 d16, {d16, d17, d18}, d20 @ encoding: [0xf0,0xff,0xa4,0x0a]
13 @ CHECK: vtbl.8 d16, {d16, d17, d18, d19}, d20 @ encoding: [0xf0,0xff,0xa4,0x0b]
/external/mesa3d/src/gallium/auxiliary/pipebuffer/
Dpb_buffer.h111 const struct pb_vtbl *vtbl; member
169 return buf->vtbl->map(buf, flags, flush_ctx); in pb_map()
180 buf->vtbl->unmap(buf); in pb_unmap()
196 assert(buf->vtbl->get_base_buffer); in pb_get_base_buffer()
197 buf->vtbl->get_base_buffer(buf, base_buf, offset); in pb_get_base_buffer()
209 assert(buf->vtbl->validate); in pb_validate()
210 return buf->vtbl->validate(buf, vl, flags); in pb_validate()
220 assert(buf->vtbl->fence); in pb_fence()
221 buf->vtbl->fence(buf, fence); in pb_fence()
232 buf->vtbl->destroy(buf); in pb_destroy()
/external/mesa3d/src/gallium/auxiliary/util/
Du_resource.c17 return ur->vtbl->resource_get_handle(screen, resource, handle); in u_resource_get_handle_vtbl()
24 ur->vtbl->resource_destroy(screen, resource); in u_resource_destroy_vtbl()
34 return ur->vtbl->get_transfer(context, resource, level, usage, box); in u_get_transfer_vtbl()
41 ur->vtbl->transfer_destroy(pipe, transfer); in u_transfer_destroy_vtbl()
48 return ur->vtbl->transfer_map(pipe, transfer); in u_transfer_map_vtbl()
56 ur->vtbl->transfer_flush_region(pipe, transfer, box); in u_transfer_flush_region_vtbl()
63 ur->vtbl->transfer_unmap(pipe, transfer); in u_transfer_unmap_vtbl()
76 ur->vtbl->transfer_inline_write(pipe, in u_transfer_inline_write_vtbl()
/external/libhevc/common/arm/
Dihevc_intra_pred_luma_mode_3_to_9.s202 vtbl.8 d12, {d0,d1}, d8 @load from ref_main_idx (row 0)
205 vtbl.8 d13, {d0,d1}, d9 @load from ref_main_idx + 1 (row 0)
209 vtbl.8 d16, {d0,d1}, d4 @load from ref_main_idx (row 1)
213 vtbl.8 d17, {d0,d1}, d5 @load from ref_main_idx + 1 (row 1)
219 vtbl.8 d14, {d0,d1}, d8 @load from ref_main_idx (row 2)
223 vtbl.8 d15, {d0,d1}, d9 @load from ref_main_idx + 1 (row 2)
230 vtbl.8 d10, {d0,d1}, d4 @load from ref_main_idx (row 3)
234 vtbl.8 d11, {d0,d1}, d5 @load from ref_main_idx + 1 (row 3)
241 vtbl.8 d12, {d0,d1}, d8 @load from ref_main_idx (row 4)
245 vtbl.8 d13, {d0,d1}, d9 @load from ref_main_idx + 1 (row 4)
[all …]
Dihevc_intra_pred_filters_luma_mode_11_to_17.s312 vtbl.8 d12, {d0,d1}, d8 @load from ref_main_idx (row 0)
315 vtbl.8 d13, {d0,d1}, d9 @load from ref_main_idx + 1 (row 0)
319 vtbl.8 d16, {d0,d1}, d4 @load from ref_main_idx (row 1)
323 vtbl.8 d17, {d0,d1}, d5 @load from ref_main_idx + 1 (row 1)
329 vtbl.8 d14, {d0,d1}, d8 @load from ref_main_idx (row 2)
333 vtbl.8 d15, {d0,d1}, d9 @load from ref_main_idx + 1 (row 2)
340 vtbl.8 d10, {d0,d1}, d4 @load from ref_main_idx (row 3)
344 vtbl.8 d11, {d0,d1}, d5 @load from ref_main_idx + 1 (row 3)
351 vtbl.8 d12, {d0,d1}, d8 @load from ref_main_idx (row 4)
355 vtbl.8 d13, {d0,d1}, d9 @load from ref_main_idx + 1 (row 4)
[all …]
Dihevc_intra_pred_chroma_mode_3_to_9.s197 vtbl.8 d12, {d0,d1,d2,d3}, d8 @load from ref_main_idx (row 0)
200 vtbl.8 d13, {d0,d1,d2,d3}, d9 @load from ref_main_idx + 1 (row 0)
206 vtbl.8 d16, {d0,d1,d2,d3}, d4 @load from ref_main_idx (row 1)
210 vtbl.8 d17, {d0,d1,d2,d3}, d5 @load from ref_main_idx + 1 (row 1)
216 vtbl.8 d14, {d0,d1,d2,d3}, d8 @load from ref_main_idx (row 2)
220 vtbl.8 d15, {d0,d1,d2,d3}, d9 @load from ref_main_idx + 1 (row 2)
227 vtbl.8 d10, {d0,d1,d2,d3}, d4 @load from ref_main_idx (row 3)
231 vtbl.8 d11, {d0,d1,d2,d3}, d5 @load from ref_main_idx + 1 (row 3)
238 vtbl.8 d12, {d0,d1,d2,d3}, d8 @load from ref_main_idx (row 4)
242 vtbl.8 d13, {d0,d1,d2,d3}, d9 @load from ref_main_idx + 1 (row 4)
[all …]
Dihevc_intra_pred_filters_chroma_mode_11_to_17.s310 vtbl.8 d12, {d0,d1,d2,d3}, d8 @load from ref_main_idx (row 0)
313 vtbl.8 d13, {d0,d1,d2,d3}, d9 @load from ref_main_idx + 1 (row 0)
320 vtbl.8 d16, {d0,d1,d2,d3}, d4 @load from ref_main_idx (row 1)
324 vtbl.8 d17, {d0,d1,d2,d3}, d5 @load from ref_main_idx + 1 (row 1)
330 vtbl.8 d14, {d0,d1,d2,d3}, d8 @load from ref_main_idx (row 2)
334 vtbl.8 d15, {d0,d1,d2,d3}, d9 @load from ref_main_idx + 1 (row 2)
341 vtbl.8 d10, {d0,d1,d2,d3}, d4 @load from ref_main_idx (row 3)
345 vtbl.8 d11, {d0,d1,d2,d3}, d5 @load from ref_main_idx + 1 (row 3)
352 vtbl.8 d12, {d0,d1,d2,d3}, d8 @load from ref_main_idx (row 4)
356 vtbl.8 d13, {d0,d1,d2,d3}, d9 @load from ref_main_idx + 1 (row 4)
[all …]
/external/mesa3d/src/mesa/drivers/dri/radeon/
Dradeon_context.c148 radeon->vtbl.get_lock = r100_get_lock; in r100_init_vtbl()
149 radeon->vtbl.update_viewport_offset = radeonUpdateViewportOffset; in r100_init_vtbl()
150 radeon->vtbl.emit_cs_header = r100_vtbl_emit_cs_header; in r100_init_vtbl()
151 radeon->vtbl.swtcl_flush = r100_swtcl_flush; in r100_init_vtbl()
152 radeon->vtbl.pre_emit_state = r100_vtbl_pre_emit_state; in r100_init_vtbl()
153 radeon->vtbl.fallback = radeonFallback; in r100_init_vtbl()
154 radeon->vtbl.free_context = r100_vtbl_free_context; in r100_init_vtbl()
155 radeon->vtbl.emit_query_finish = r100_emit_query_finish; in r100_init_vtbl()
156 radeon->vtbl.check_blit = r100_check_blit; in r100_init_vtbl()
157 radeon->vtbl.blit = r100_blit; in r100_init_vtbl()
[all …]
Dradeon_common.c139 if (rmesa->vtbl.update_scissor) in radeonUpdateScissor()
140 rmesa->vtbl.update_scissor(ctx); in radeonUpdateScissor()
216 radeon->vtbl.fallback(ctx, RADEON_FALLBACK_DRAW_BUFFER, GL_TRUE); in radeon_draw_buffer()
262 radeon->vtbl.fallback(ctx, RADEON_FALLBACK_DRAW_BUFFER, GL_TRUE); in radeon_draw_buffer()
264 radeon->vtbl.fallback(ctx, RADEON_FALLBACK_DRAW_BUFFER, GL_FALSE); in radeon_draw_buffer()
270 radeon->vtbl.fallback(ctx, RADEON_FALLBACK_DEPTH_BUFFER, GL_FALSE); in radeon_draw_buffer()
272 radeon->vtbl.fallback(ctx, RADEON_FALLBACK_DEPTH_BUFFER, GL_TRUE); in radeon_draw_buffer()
275 radeon->vtbl.fallback(ctx, RADEON_FALLBACK_DEPTH_BUFFER, GL_FALSE); in radeon_draw_buffer()
282 radeon->vtbl.fallback(ctx, RADEON_FALLBACK_STENCIL_BUFFER, GL_FALSE); in radeon_draw_buffer()
287 radeon->vtbl.fallback(ctx, RADEON_FALLBACK_STENCIL_BUFFER, GL_TRUE); in radeon_draw_buffer()
[all …]
Dradeon_pixel_read.c109 !radeon->vtbl.check_blit(dst_format, rrb->pitch / rrb->cpp) || !radeon->vtbl.blit) { in do_blit_readpixels()
158 if (radeon->vtbl.blit(ctx, in do_blit_readpixels()
Dradeon_tex_copy.c57 if (!radeon->vtbl.blit) { in do_copy_texsubimage()
101 if (!radeon->vtbl.check_blit(dst_mesaformat, rrb->pitch / rrb->cpp)) { in do_copy_texsubimage()
128 return radeon->vtbl.blit(ctx, rrb->bo, src_offset, src_mesaformat, rrb->pitch/rrb->cpp, in do_copy_texsubimage()
/external/mesa3d/src/mesa/drivers/dri/r200/
Dr200_context.c183 radeon->vtbl.get_lock = r200_get_lock; in r200_init_vtbl()
184 radeon->vtbl.update_viewport_offset = r200UpdateViewportOffset; in r200_init_vtbl()
185 radeon->vtbl.emit_cs_header = r200_vtbl_emit_cs_header; in r200_init_vtbl()
186 radeon->vtbl.swtcl_flush = r200_swtcl_flush; in r200_init_vtbl()
187 radeon->vtbl.fallback = r200Fallback; in r200_init_vtbl()
188 radeon->vtbl.update_scissor = r200_vtbl_update_scissor; in r200_init_vtbl()
189 radeon->vtbl.emit_query_finish = r200_emit_query_finish; in r200_init_vtbl()
190 radeon->vtbl.check_blit = r200_check_blit; in r200_init_vtbl()
191 radeon->vtbl.blit = r200_blit; in r200_init_vtbl()
192 radeon->vtbl.is_format_renderable = radeonIsFormatRenderable; in r200_init_vtbl()
Dradeon_common.c139 if (rmesa->vtbl.update_scissor) in radeonUpdateScissor()
140 rmesa->vtbl.update_scissor(ctx); in radeonUpdateScissor()
216 radeon->vtbl.fallback(ctx, RADEON_FALLBACK_DRAW_BUFFER, GL_TRUE); in radeon_draw_buffer()
262 radeon->vtbl.fallback(ctx, RADEON_FALLBACK_DRAW_BUFFER, GL_TRUE); in radeon_draw_buffer()
264 radeon->vtbl.fallback(ctx, RADEON_FALLBACK_DRAW_BUFFER, GL_FALSE); in radeon_draw_buffer()
270 radeon->vtbl.fallback(ctx, RADEON_FALLBACK_DEPTH_BUFFER, GL_FALSE); in radeon_draw_buffer()
272 radeon->vtbl.fallback(ctx, RADEON_FALLBACK_DEPTH_BUFFER, GL_TRUE); in radeon_draw_buffer()
275 radeon->vtbl.fallback(ctx, RADEON_FALLBACK_DEPTH_BUFFER, GL_FALSE); in radeon_draw_buffer()
282 radeon->vtbl.fallback(ctx, RADEON_FALLBACK_STENCIL_BUFFER, GL_FALSE); in radeon_draw_buffer()
287 radeon->vtbl.fallback(ctx, RADEON_FALLBACK_STENCIL_BUFFER, GL_TRUE); in radeon_draw_buffer()
[all …]
Dradeon_pixel_read.c109 !radeon->vtbl.check_blit(dst_format, rrb->pitch / rrb->cpp) || !radeon->vtbl.blit) { in do_blit_readpixels()
158 if (radeon->vtbl.blit(ctx, in do_blit_readpixels()
Dradeon_tex_copy.c57 if (!radeon->vtbl.blit) { in do_copy_texsubimage()
101 if (!radeon->vtbl.check_blit(dst_mesaformat, rrb->pitch / rrb->cpp)) { in do_copy_texsubimage()
128 return radeon->vtbl.blit(ctx, rrb->bo, src_offset, src_mesaformat, rrb->pitch/rrb->cpp, in do_copy_texsubimage()
/external/mesa3d/src/mesa/drivers/dri/i915/
Di915_vtbl.c805 intel->vtbl.set_draw_region(intel, &colorRegion, depthRegion, in i915_update_draw_buffer()
871 i915->intel.vtbl.check_vertex_size = i915_check_vertex_size; in i915InitVtbl()
872 i915->intel.vtbl.destroy = i915_destroy_context; in i915InitVtbl()
873 i915->intel.vtbl.emit_state = i915_emit_state; in i915InitVtbl()
874 i915->intel.vtbl.new_batch = i915_new_batch; in i915InitVtbl()
875 i915->intel.vtbl.reduced_primitive_state = i915_reduced_primitive_state; in i915InitVtbl()
876 i915->intel.vtbl.render_start = i915_render_start; in i915InitVtbl()
877 i915->intel.vtbl.render_prevalidate = i915_render_prevalidate; in i915InitVtbl()
878 i915->intel.vtbl.set_draw_region = i915_set_draw_region; in i915InitVtbl()
879 i915->intel.vtbl.update_draw_buffer = i915_update_draw_buffer; in i915InitVtbl()
[all …]
Di830_vtbl.c834 intel->vtbl.set_draw_region(intel, colorRegions, depthRegion, in i830_update_draw_buffer()
893 i830->intel.vtbl.check_vertex_size = i830_check_vertex_size; in i830InitVtbl()
894 i830->intel.vtbl.destroy = i830_destroy_context; in i830InitVtbl()
895 i830->intel.vtbl.emit_state = i830_emit_state; in i830InitVtbl()
896 i830->intel.vtbl.new_batch = i830_new_batch; in i830InitVtbl()
897 i830->intel.vtbl.reduced_primitive_state = i830_reduced_primitive_state; in i830InitVtbl()
898 i830->intel.vtbl.set_draw_region = i830_set_draw_region; in i830InitVtbl()
899 i830->intel.vtbl.update_draw_buffer = i830_update_draw_buffer; in i830InitVtbl()
900 i830->intel.vtbl.update_texture_state = i830UpdateTextureState; in i830InitVtbl()
901 i830->intel.vtbl.render_start = i830_render_start; in i830InitVtbl()
[all …]
Dintel_batchbuffer.c155 if (intel->vtbl.debug_batch != NULL) in do_batch_dump()
156 intel->vtbl.debug_batch(intel); in do_batch_dump()
189 if (unlikely(INTEL_DEBUG & DEBUG_AUB) && intel->vtbl.annotate_aub) in do_flush_locked()
190 intel->vtbl.annotate_aub(intel); in do_flush_locked()
208 intel->vtbl.new_batch(intel); in do_flush_locked()
233 if (intel->vtbl.finish_batch) in _intel_batchbuffer_flush()
234 intel->vtbl.finish_batch(intel); in _intel_batchbuffer_flush()
/external/mesa3d/src/mesa/drivers/dri/intel/
Dintel_batchbuffer.c155 if (intel->vtbl.debug_batch != NULL) in do_batch_dump()
156 intel->vtbl.debug_batch(intel); in do_batch_dump()
189 if (unlikely(INTEL_DEBUG & DEBUG_AUB) && intel->vtbl.annotate_aub) in do_flush_locked()
190 intel->vtbl.annotate_aub(intel); in do_flush_locked()
208 intel->vtbl.new_batch(intel); in do_flush_locked()
233 if (intel->vtbl.finish_batch) in _intel_batchbuffer_flush()
234 intel->vtbl.finish_batch(intel); in _intel_batchbuffer_flush()
/external/mesa3d/src/gallium/drivers/i915/
Di915_resource.h100 assert(tex->b.vtbl == &i915_texture_vtbl); in i915_texture()
107 assert(tex->b.vtbl == &i915_buffer_vtbl); in i915_buffer()
/external/llvm/test/CodeGen/ARM/
Dshuffle.ll8 ; CHECK: vtbl
15 ; CHECK: vtbl
/external/llvm/test/Transforms/InstCombine/
Dalias-recursion.ll10 @vtbl = alias getelementptr inbounds ([1 x i8*], [1 x i8*]* @0, i32 0, i32 0)
21 …%A = phi i32 (%class.A*)** [ bitcast (i8** @vtbl to i32 (%class.A*)**), %for.body ], [ null, %entr…

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