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/external/llvm/test/MC/Mips/msa/
Dtest_2rf.s3 # CHECK: fclass.w $w26, $w12 # encoding: [0x7b,0x20,0x66,0x9e]
10 # CHECK: ffint_s.d $w12, $w15 # encoding: [0x7b,0x3d,0x7b,0x1e]
14 # CHECK: ffql.d $w12, $w13 # encoding: [0x7b,0x35,0x6b,0x1e]
23 # CHECK: frsqrt.w $w12, $w17 # encoding: [0x7b,0x28,0x8b,0x1e]
26 # CHECK: fsqrt.d $w15, $w12 # encoding: [0x7b,0x27,0x63,0xde]
32 # CHECK: ftrunc_s.d $w12, $w27 # encoding: [0x7b,0x23,0xdb,0x1e]
36 fclass.w $w26, $w12
43 ffint_s.d $w12, $w15
47 ffql.d $w12, $w13
56 frsqrt.w $w12, $w17
[all …]
Dtest_3r.s26 # CHECK: asub_s.d $w13, $w12, $w12 # encoding: [0x7a,0x6c,0x63,0x51]
37 # CHECK: ave_u.w $w11, $w12, $w11 # encoding: [0x7a,0xcb,0x62,0xd0]
54 # CHECK: binsl.d $w23, $w20, $w12 # encoding: [0x7b,0x6c,0xa5,0xcd]
64 # CHECK: bset.h $w14, $w12, $w6 # encoding: [0x7a,0x26,0x63,0x8d]
65 # CHECK: bset.w $w31, $w9, $w12 # encoding: [0x7a,0x4c,0x4f,0xcd]
82 # CHECK: clt_s.d $w7, $w30, $w12 # encoding: [0x79,0x6c,0xf1,0xcf]
102 # CHECK: dpadd_s.w $w10, $w1, $w12 # encoding: [0x79,0x4c,0x0a,0x93]
107 # CHECK: dpsub_s.h $w4, $w11, $w12 # encoding: [0x7a,0x2c,0x59,0x13]
109 # CHECK: dpsub_s.d $w31, $w12, $w28 # encoding: [0x7a,0x7c,0x67,0xd3]
116 # CHECK: hadd_u.h $w12, $w29, $w17 # encoding: [0x7a,0xb1,0xeb,0x15]
[all …]
Dtest_i5.s9 # CHECK: ceqi.w $w12, $w1, -1 # encoding: [0x78,0x5f,0x0b,0x07]
11 # CHECK: clei_s.b $w12, $w16, 1 # encoding: [0x7a,0x01,0x83,0x07]
21 # CHECK: clti_s.w $w12, $w12, 11 # encoding: [0x79,0x4b,0x63,0x07]
41 # CHECK: mini_u.w $w11, $w12, 26 # encoding: [0x7a,0xda,0x62,0xc6]
45 # CHECK: subvi.w $w12, $w10, 11 # encoding: [0x78,0xcb,0x53,0x06]
54 ceqi.w $w12, $w1, -1
56 clei_s.b $w12, $w16, 1
66 clti_s.w $w12, $w12, 11
86 mini_u.w $w11, $w12, 26
90 subvi.w $w12, $w10, 11
Dset-msa-directive.s4 # CHECK: addvi.b $w14, $w12, 14
8 # CHECK: subvi.b $w14, $w12, 14
14 addvi.b $w14, $w12, 14
19 subvi.b $w14, $w12, 14
Dtest_3rf.s53 # CHECK: fslt.w $w12, $w5, $w6 # encoding: [0x7b,0x06,0x2b,0x1a]
55 # CHECK: fsne.w $w30, $w1, $w12 # encoding: [0x7a,0xcc,0x0f,0x9c]
58 # CHECK: fsor.d $w12, $w24, $w11 # encoding: [0x7a,0x6b,0xc3,0x1c]
76 # CHECK: maddr_q.w $w29, $w12, $w16 # encoding: [0x7b,0x70,0x67,0x5c]
79 # CHECK: msubr_q.h $w12, $w21, $w11 # encoding: [0x7b,0x8b,0xab,0x1c]
136 fslt.w $w12, $w5, $w6
138 fsne.w $w30, $w1, $w12
141 fsor.d $w12, $w24, $w11
159 maddr_q.w $w29, $w12, $w16
162 msubr_q.h $w12, $w21, $w11
Dtest_elm.s12 # CHECK: sldi.d $w4, $w12[0] # encoding: [0x78,0x38,0x61,0x19]
28 sldi.d $w4, $w12[0]
Dtest_mi10.s17 # CHECK: ld.w $w12, 1024($13) # encoding: [0x79,0x00,0x6b,0x22]
44 ld.w $w12, 1024($13)
Dset-msa-directive-bad.s5 …addvi.b $w14, $w12, 14 # CHECK: error: instruction requires a CPU feature not currently enabled
/external/openssh/
Dblocks.c56 M(w3 ,w1 ,w12,w4 ) \
64 M(w11,w9 ,w4 ,w12) \
65 M(w12,w10,w5 ,w13) \
67 M(w14,w12,w7 ,w15) \
118 uint64 w12 = load_bigendian(in + 96); in crypto_hashblocks_sha512() local
135 F(w12,0x72be5d74f27b896fULL) in crypto_hashblocks_sha512()
154 F(w12,0xc6e00bf33da88fc2ULL) in crypto_hashblocks_sha512()
173 F(w12,0xd192e819d6ef5218ULL) in crypto_hashblocks_sha512()
192 F(w12,0x90befffa23631e28ULL) in crypto_hashblocks_sha512()
211 F(w12,0x4cc5d4becb3e42b6ULL) in crypto_hashblocks_sha512()
/external/llvm/test/MC/Disassembler/Mips/msa/
Dtest_2rf.txt3 0x7b 0x20 0x66 0x9e # CHECK: fclass.w $w26, $w12
10 0x7b 0x3d 0x7b 0x1e # CHECK: ffint_s.d $w12, $w15
14 0x7b 0x35 0x6b 0x1e # CHECK: ffql.d $w12, $w13
23 0x7b 0x28 0x8b 0x1e # CHECK: frsqrt.w $w12, $w17
26 0x7b 0x27 0x63 0xde # CHECK: fsqrt.d $w15, $w12
32 0x7b 0x23 0xdb 0x1e # CHECK: ftrunc_s.d $w12, $w27
Dtest_3r.txt26 0x7a 0x6c 0x63 0x51 # CHECK: asub_s.d $w13, $w12, $w12
37 0x7a 0xcb 0x62 0xd0 # CHECK: ave_u.w $w11, $w12, $w11
54 0x7b 0x6c 0xa5 0xcd # CHECK: binsl.d $w23, $w20, $w12
64 0x7a 0x26 0x63 0x8d # CHECK: bset.h $w14, $w12, $w6
65 0x7a 0x4c 0x4f 0xcd # CHECK: bset.w $w31, $w9, $w12
82 0x79 0x6c 0xf1 0xcf # CHECK: clt_s.d $w7, $w30, $w12
102 0x79 0x4c 0x0a 0x93 # CHECK: dpadd_s.w $w10, $w1, $w12
107 0x7a 0x2c 0x59 0x13 # CHECK: dpsub_s.h $w4, $w11, $w12
109 0x7a 0x7c 0x67 0xd3 # CHECK: dpsub_s.d $w31, $w12, $w28
116 0x7a 0xb1 0xeb 0x15 # CHECK: hadd_u.h $w12, $w29, $w17
[all …]
Dtest_i5.txt9 0x78 0x5f 0x0b 0x07 # CHECK: ceqi.w $w12, $w1, 31
11 0x7a 0x01 0x83 0x07 # CHECK: clei_s.b $w12, $w16, 1
21 0x79 0x4b 0x63 0x07 # CHECK: clti_s.w $w12, $w12, 11
41 0x7a 0xda 0x62 0xc6 # CHECK: mini_u.w $w11, $w12, 26
45 0x78 0xcb 0x53 0x06 # CHECK: subvi.w $w12, $w10, 11
Dtest_3rf.txt53 0x7b 0x06 0x2b 0x1a # CHECK: fslt.w $w12, $w5, $w6
55 0x7a 0xcc 0x0f 0x9c # CHECK: fsne.w $w30, $w1, $w12
58 0x7a 0x6b 0xc3 0x1c # CHECK: fsor.d $w12, $w24, $w11
76 0x7b 0x70 0x67 0x5c # CHECK: maddr_q.w $w29, $w12, $w16
79 0x7b 0x8b 0xab 0x1c # CHECK: msubr_q.h $w12, $w21, $w11
/external/boringssl/linux-aarch64/crypto/sha/
Dsha1-armv8.S150 add w20,w20,w12 // future e+=X[i]
234 eor w4,w4,w12
309 eor w10,w10,w12
333 eor w12,w12,w14
337 eor w12,w12,w4
341 eor w12,w12,w9
344 ror w12,w12,#31
354 add w24,w24,w12 // future e+=X[i]
377 eor w15,w15,w12
433 eor w4,w4,w12
[all …]
Dsha256-armv8.S191 eor w12,w26,w26,ror#14
197 eor w16,w16,w12,ror#11 // Sigma1(e)
198 ror w12,w22,#2
205 eor w17,w12,w17,ror#13 // Sigma0(a)
212 ldp w11,w12,[x1],#2*4
259 rev w12,w12 // 9
268 add w26,w26,w12 // h+=X[i]
438 add w3,w3,w12
478 str w12,[sp,#4]
485 ror w12,w27,#2
[all …]
/external/libhevc/common/arm64/
Dihevc_sao_edge_offset_class0_chroma.s102 LDRH w12,[x20] //pu1_src_top[wd - 1]
106 STRH w12,[x4] //*pu1_src_top_left = pu1_src_top[wd - 1]
143 LDRB w12,[x7] //pu1_avail[0]
144 mov v3.b[0], w12 //vsetq_lane_s8(pu1_avail[0], au1_mask, 0)
145 mov v3.b[1], w12 //vsetq_lane_s8(pu1_avail[0], au1_mask, 1)
150 mov v3.h[0], w12 //au1_mask = vsetq_lane_s8(-1, au1_mask, 0)
155 LDRB w12,[x7,#1] //pu1_avail[1]
156 mov v3.b[14], w12 //au1_mask = vsetq_lane_s8(pu1_avail[1], au1_mask, 14)
157 mov v3.b[15], w12 //au1_mask = vsetq_lane_s8(pu1_avail[1], au1_mask, 15)
330 LDRB w12,[x7] //pu1_avail[0]
[all …]
Dihevc_sao_edge_offset_class0.s89 LDRB w12,[x11] //pu1_src_top[wd - 1]
97 STRB w12,[x4] //*pu1_src_top_left = pu1_src_top[wd - 1]
125 LDRB w12,[x7] //pu1_avail[0]
126 mov v3.b[0], w12 //vsetq_lane_s8(pu1_avail[0], au1_mask, 0)
131 mov v3.b[0], w12 //au1_mask = vsetq_lane_s8(-1, au1_mask, 0)
136 LDRB w12,[x7,#1] //pu1_avail[1]
137 mov v3.b[15], w12 //au1_mask = vsetq_lane_s8(pu1_avail[1], au1_mask, 15)
273 LDRB w12,[x7] //pu1_avail[0]
274 mov v3.b[0], w12 //vsetq_lane_s8(pu1_avail[0], au1_mask, 0)
279 mov v3.b[0], w12 //au1_mask = vsetq_lane_s8(-1, au1_mask, 0)
Dihevc_intra_pred_luma_vert.s182 ldrb w12, [x6] //src[2nt+1]
183 sxtw x12,w12
188 dup v24.16b,w12 //src[2nt+1]
189 dup v30.8h,w12
322 ldrb w12, [x6] //src[2nt+1]
323 sxtw x12,w12
328 dup v24.8b,w12 //src[2nt+1]
329 dup v30.8h,w12
/external/llvm/test/CodeGen/Mips/
Dno-odd-spreg-msa.ll13 ; Clobber all except $f12/$w12 and $f13
16 ; allocator will choose $f12/$w12 for the vector and $f13 for the float to
47 ; Clobber all except $f12/$w12 and $f13
50 ; allocator will choose $f12/$w12 for the vector and $f13 for the float to
77 %1 = call <4 x float> asm sideeffect "move.v $0, $1", "={$w13},{$w12}" (<4 x float> %0)
85 ; must move it to $f12/$w12.
94 ; ALL: ld.w $w12, 0($[[R0]])
95 ; ALL: move.v $w[[W0:13]], $w12
105 %1 = call <4 x float> asm sideeffect "move.v $0, $1", "={$w13},{$w12}" (<4 x float> %0)
122 ; ALL: ld.w $w12, 0($[[R0]])
/external/llvm/test/MC/Disassembler/AArch64/
Darm64-arithmetic.txt97 # CHECK: add w12, w13, w14
99 # CHECK: add w12, w13, w14, lsl #12
101 # CHECK: add w12, w13, w14, lsr #10
103 # CHECK: add w12, w13, w14, asr #7
115 # CHECK: sub w12, w13, w14
117 # CHECK: sub w12, w13, w14, lsl #12
119 # CHECK: sub w12, w13, w14, lsr #10
121 # CHECK: sub w12, w13, w14, asr #7
133 # CHECK: adds w12, w13, w14
135 # CHECK: adds w12, w13, w14, lsl #12
[all …]
/external/llvm/test/MC/AArch64/
Dbasic-a64-diagnostics.s395 cmn w11, w12, lsr #-1
396 cmn w11, w12, lsr #32
444 cmp w11, w12, lsr #-1
445 cmp w11, w12, lsr #32
493 neg w11, w12, lsr #-1
494 neg w11, w12, lsr #32
542 negs w11, w12, lsr #-1
543 negs w11, w12, lsr #32
757 sbfm w12, x9, #0, #0
890 sbfiz w11, w12, #32, #0
[all …]
Darm64-arithmetic-encoding.s106 add w12, w13, w14
108 add w12, w13, w14, lsl #12
113 ; CHECK: add w12, w13, w14 ; encoding: [0xac,0x01,0x0e,0x0b]
115 ; CHECK: add w12, w13, w14, lsl #12 ; encoding: [0xac,0x31,0x0e,0x0b]
120 sub w12, w13, w14
122 sub w12, w13, w14, lsl #12
127 ; CHECK: sub w12, w13, w14 ; encoding: [0xac,0x01,0x0e,0x4b]
129 ; CHECK: sub w12, w13, w14, lsl #12 ; encoding: [0xac,0x31,0x0e,0x4b]
134 adds w12, w13, w14
136 adds w12, w13, w14, lsl #12
[all …]
Dbasic-a64-instructions.s629 cmn w12, w13, lsr #0
689 cmp w12, w13, lsr #0
757 neg w12, w11, asr #31
815 negs w12, w11, asr #31
924 ngc w3, w12
938 ngcs w3, w12
959 sbfm w12, w9, #0, #0
1036 sbfiz w11, w12, #31, #1
1053 sbfx w11, w12, #31, #1
1070 bfi w11, w12, #31, #1
[all …]
/external/v8/test/cctest/
Dtest-disasm-arm64.cc270 COMPARE(add(w12, w13, Operand(0xfff000)), in TEST_()
300 COMPARE(sub(w12, w13, Operand(0xfff000)), in TEST_()
325 COMPARE(add(w12, w13, Operand(w14, LSR, 3)), "add w12, w13, w14, lsr #3"); in TEST_()
351 COMPARE(sub(w12, w13, Operand(w14, LSR, 3)), "sub w12, w13, w14, lsr #3"); in TEST_()
433 COMPARE(sbc(w12, w13, Operand(w14)), "sbc w12, w13, w14"); in TEST_()
564 COMPARE(extr(w12, w13, w13, 10), "ror w12, w13, #10"); in TEST_()
658 COMPARE(orn(w11, w12, Operand(0x40004000)), in TEST_()
704 COMPARE(and_(w12, w13, Operand(w14, ROR, 4)), "and w12, w13, w14, ror #4"); in TEST_()
716 COMPARE(orr(w12, w13, Operand(w14, ROR, 12)), "orr w12, w13, w14, ror #12"); in TEST_()
728 COMPARE(eor(w12, w13, Operand(w14, ROR, 20)), "eor w12, w13, w14, ror #20"); in TEST_()
[all …]
/external/libavc/common/armv8/
Dih264_weighted_bi_pred_av8.s157 cmp w12, #16
159 cmp w12, #8 //check if wd is 8
435 ldr w12, [sp, #112] //Load wd in x12
437 sxtw x12, w12
442 cmp w12, #8 //check if wd is 8
444 cmp w12, #4 //check if wd is 4

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