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Searched refs:writeback (Results 1 – 22 of 22) sorted by relevance

/external/clang/lib/CodeGen/
DCGCall.h93 Writeback writeback; in addWriteback() local
94 writeback.Source = srcLV; in addWriteback()
95 writeback.Temporary = temporary; in addWriteback()
96 writeback.ToUse = toUse; in addWriteback()
97 Writebacks.push_back(writeback); in addWriteback()
DCGCall.cpp2450 const CallArgList::Writeback &writeback) { in emitWriteback() argument
2451 const LValue &srcLV = writeback.Source; in emitWriteback()
2471 llvm::Value *value = CGF.Builder.CreateLoad(writeback.Temporary); in emitWriteback()
2485 if (writeback.ToUse) { in emitWriteback()
2493 CGF.EmitARCIntrinsicUse(writeback.ToUse); in emitWriteback()
/external/llvm/test/MC/ARM/
Dthumb-diagnostics.s58 @ Invalid writeback and register lists for LDM
74 @ CHECK-ERRORS: error: writeback operator '!' expected
77 @ CHECK-ERRORS: error: writeback operator '!' not allowed when base register in register list
80 @ CHECK-ERRORS-V8: error: writeback operator '!' not allowed when base register in register list
83 @ CHECK-ERRORS-V8: error: writeback register not allowed in register list
108 @ Invalid writeback and register lists for PUSH/POP
119 @ Invalid writeback and register lists for STM
134 @ CHECK-ERRORS-V8: error: writeback operator '!' not allowed when base register in register list
137 @ CHECK-ERRORS-V8: error: writeback register not allowed in register list
Ddiagnostics.s460 @ CHECK-ERRORS: error: writeback register not allowed in register list
461 @ CHECK-ERRORS: error: writeback register not allowed in register list
462 @ CHECK-ERRORS: error: writeback register not allowed in register list
463 @ CHECK-ERRORS: error: writeback register not allowed in register list
484 @ CHECK-ERRORS: error: system STM cannot have writeback register
485 @ CHECK-ERRORS: error: writeback register only allowed on system LDM if PC in register-list
Darm-load-store-multiple-deprecated.s204 @ CHECK-V7: error: writeback register not allowed in register list
207 @ CHECK-V7: error: writeback register not allowed in register list
/external/llvm/test/MC/AArch64/
Darm64-diags.s155 ; Load pair instructions where Rt==Rt2 and writeback load/store instructions
182 ; CHECK-ERRORS: error: unpredictable LDP instruction, writeback base is also a destination
185 ; CHECK-ERRORS: error: unpredictable LDP instruction, writeback base is also a destination
188 ; CHECK-ERRORS: error: unpredictable LDP instruction, writeback base is also a destination
191 ; CHECK-ERRORS: error: unpredictable LDP instruction, writeback base is also a destination
224 ; CHECK-ERRORS: error: unpredictable LDR instruction, writeback base is also a source
227 ; CHECK-ERRORS: error: unpredictable LDR instruction, writeback base is also a source
230 ; CHECK-ERRORS: error: unpredictable LDR instruction, writeback base is also a source
233 ; CHECK-ERRORS: error: unpredictable LDR instruction, writeback base is also a source
236 ; CHECK-ERRORS: error: unpredictable STR instruction, writeback base is also a source
[all …]
/external/kernel-headers/original/uapi/drm/
Dexynos_drm.h183 __u32 writeback; member
/external/llvm/test/MC/Disassembler/AArch64/
Dbasic-a64-unpredictable.txt84 # Also unpredictable if writeback clashes with either transfer register
/external/llvm/lib/Target/AArch64/
DAArch64SchedCyclone.td61 // consumes the pipe for one cycle at issue and another cycle at writeback.
90 // but only consume the pipe for one cycle at issue and a cycle at writeback.
203 // The ID pipe is consumed for 2 cycles: issue and writeback.
210 // The ID pipe is consumed for 2 cycles: issue and writeback.
626 // Only the first WriteVLD and WriteAdr for writeback matches def operands.
767 // Only the WriteAdr for writeback matches a def operands.
/external/llvm/lib/Target/ARM/Disassembler/
DARMDisassembler.cpp1532 bool writeback = (P == 0) || (W == 1); in DecodeAddrMode2IdxInstruction() local
1534 if (P && writeback) in DecodeAddrMode2IdxInstruction()
1536 else if (!P && writeback) in DecodeAddrMode2IdxInstruction()
1539 if (writeback && (Rn == 15 || Rn == Rt)) in DecodeAddrMode2IdxInstruction()
1639 bool writeback = (W == 1) | (P == 0); in DecodeAddrMode3Instruction() local
1661 if (writeback && (Rn == 15 || Rn == Rt || Rn == Rt2)) in DecodeAddrMode3Instruction()
1675 if (writeback && (Rn == 15 || Rn == Rt)) in DecodeAddrMode3Instruction()
1692 if (!type && writeback && Rn == 15) in DecodeAddrMode3Instruction()
1694 if (writeback && (Rn == Rt || Rn == Rt2)) in DecodeAddrMode3Instruction()
1709 if (!type && writeback && (Rn == 15 || Rn == Rt)) in DecodeAddrMode3Instruction()
[all …]
/external/llvm/lib/Target/ARM/
DARMScheduleA9.td448 // register file writeback!).
2313 // A9WriteAdr consumes AGU regardless address writeback. But it's
2323 // Store either has no def operands, or the one def for address writeback.
2341 // Load multiple with address writeback has an extra def operand in
2345 // resources are identical, For stores only the address writeback
2360 // Note: Unlike VLDM, VLD1 expects the writeback operand after the
2381 // address writeback.
DARMInstrNEON.td698 // ...with address register writeback:
854 // ...with address register writeback:
927 // ...with address register writeback:
986 // ...with address register writeback:
1111 // ...with address register writeback:
1174 // ...with address register writeback:
1245 // ...with address register writeback:
1322 // ...with address register writeback:
1409 // ...with address register writeback:
1484 // ...with address register writeback:
[all …]
DARMInstrVFP.td128 let Inst{21} = 0; // No writeback
156 let Inst{21} = 0; // No writeback
251 let Inst{21} = 0; // No writeback
DARMInstrThumb2.td1715 let Inst{21} = 0; // No writeback
1745 let Inst{21} = 0; // No writeback
1784 let Inst{21} = 0; // No writeback
1820 let Inst{21} = 0; // No writeback
DARMInstrInfo.td3063 let Inst{21} = 0; // No writeback
3083 let Inst{21} = 0; // No writeback
3103 let Inst{21} = 0; // No writeback
3123 let Inst{21} = 0; // No writeback
DARMInstrThumb.td744 // There is no non-writeback version of STM for Thumb.
DARMScheduleSwift.td1128 // Plain load without writeback.
/external/llvm/test/MC/Disassembler/ARM/
Dinvalid-thumbv7.txt359 # 32-bit Thumb STM instructions cannot have a writeback register which appears
/external/clang/test/CodeGenObjCXX/
Darc.mm281 // a non-dependent message send that requires writeback.
/external/clang/docs/
DAutomaticReferenceCounting.rst957 * the conversion is a well-formed :ref:`pass-by-writeback
1002 Passing to an out parameter by writeback
1007 candidate for :arc-term:`pass-by-writeback`` if:
1013 a pass-by-writeback is always worse than an implicit conversion sequence not
1014 requiring a pass-by-writeback.
1016 The pass-by-writeback is ill-formed if the argument expression does not have a
1033 below, where their store to the writeback temporary is not immediately seen
1036 A pass-by-writeback is evaluated as follows:
1040 and no further work is required for the pass-by-writeback.
1129 caution in the following rules about writeback.
/external/valgrind/none/tests/arm/
Dvfp.stdout.exp904 ---- VLDM (Increment After, writeback) ----
950 ---- VSTM (Increment After, no writeback) ----
983 ---- VSTM (Increment After, writeback) ----
/external/e2fsprogs/
DRELEASE-NOTES2884 default data=ordered or data=writeback modes. However, if a block