Searched refs:A0 (Results 1 – 10 of 10) sorted by relevance
| /art/compiler/trampolines/ |
| D | trampoline_compiler.cc | 102 __ LoadFromOffset(kLoadWord, T9, A0, offset.Int32Value()); in CreateTrampoline()
105 __ LoadFromOffset(kLoadWord, T9, A0, JNIEnvExt::SelfOffset().Int32Value()); in CreateTrampoline()
131 __ LoadFromOffset(kLoadDoubleword, T9, A0, offset.Int32Value()); in CreateTrampoline()
134 __ LoadFromOffset(kLoadDoubleword, T9, A0, JNIEnvExt::SelfOffset().Int32Value()); in CreateTrampoline()
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| /art/compiler/jni/quick/mips/ |
| D | calling_convention_mips.cc | 64 return MipsManagedRegister::FromCoreRegister(A0); in MethodRegister()
187 A0, A1, A2, A3
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| /art/compiler/jni/quick/mips64/ |
| D | calling_convention_mips64.cc | 27 A0, A1, A2, A3, A4, A5, A6, A7
68 return Mips64ManagedRegister::FromGpuRegister(A0); in MethodRegister()
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| /art/runtime/arch/mips/ |
| D | registers_mips.h | 34 A0 = 4, // Arguments. enumerator
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| /art/runtime/arch/mips64/ |
| D | registers_mips64.h | 34 A0 = 4, // Arguments. enumerator
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| D | context_mips64.cc | 77 gprs_[A0] = nullptr; in SmashCallerSaves()
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| /art/compiler/optimizing/ |
| D | code_generator_mips64.h | 48 { A0, A1, A2, A3, A4, A5, A6, A7 };
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| D | code_generator_mips64.cc | 36 static constexpr GpuRegister kMethodRegisterArgument = A0;
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| /art/compiler/utils/mips/ |
| D | assembler_mips.cc | 975 __ Move(A0, scratch_.AsCoreRegister()); in Emit()
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| /art/compiler/utils/mips64/ |
| D | assembler_mips64.cc | 1544 __ Move(A0, scratch_.AsGpuRegister()); in Emit()
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