| /art/compiler/dex/quick/arm/ |
| D | codegen_arm.h | 180 void GenSelectConst32(RegStorage left_op, RegStorage right_op, ConditionCode code,
198 LIR* OpCmpBranch(ConditionCode cond, RegStorage src1, RegStorage src2, LIR* target);
199 LIR* OpCmpImmBranch(ConditionCode cond, RegStorage reg, int check_value, LIR* target);
200 LIR* OpCondBranch(ConditionCode cc, LIR* target);
201 LIR* OpDecAndBranch(ConditionCode c_code, RegStorage reg, LIR* target);
203 LIR* OpIT(ConditionCode cond, const char* guide);
215 LIR* OpCondRegReg(OpKind op, ConditionCode cc, RegStorage r_dest, RegStorage r_src);
231 ArmConditionCode ArmConditionEncoding(ConditionCode code);
285 ConditionCode ccode);
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| D | int_arm.cc | 35 LIR* ArmMir2Lir::OpCmpBranch(ConditionCode cond, RegStorage src1, RegStorage src2, LIR* target) { in OpCmpBranch()
50 LIR* ArmMir2Lir::OpIT(ConditionCode ccode, const char* guide) { in OpIT()
167 int64_t val, ConditionCode ccode) { in GenFusedLongCmpImmBranch()
217 void ArmMir2Lir::GenSelectConst32(RegStorage left_op, RegStorage right_op, ConditionCode code, in GenSelectConst32()
251 ConditionCode ccode = mir->meta.ccode; in GenSelect()
322 ConditionCode ccode = mir->meta.ccode; in GenFusedLongCmpBranch()
380 LIR* ArmMir2Lir::OpCmpImmBranch(ConditionCode cond, RegStorage reg, int check_value, LIR* target) { in OpCmpImmBranch()
1182 LIR* ArmMir2Lir::OpDecAndBranch(ConditionCode c_code, RegStorage reg, LIR* target) { in OpDecAndBranch()
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| D | fp_arm.cc | 264 ConditionCode ccode = mir->meta.ccode; in GenFusedFPCmpBranch()
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| D | utility_arm.cc | 263 LIR* ArmMir2Lir::OpCondBranch(ConditionCode cc, LIR* target) { in OpCondBranch()
434 LIR* ArmMir2Lir::OpCondRegReg(OpKind op, ConditionCode cc, RegStorage r_dest, RegStorage r_src) { in OpCondRegReg()
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| D | target_arm.cc | 243 ArmConditionCode ArmMir2Lir::ArmConditionEncoding(ConditionCode ccode) { in ArmConditionEncoding()
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| /art/compiler/dex/quick/arm64/ |
| D | codegen_arm64.h | 85 LIR* OpCmpMemImmBranch(ConditionCode cond, RegStorage temp_reg, RegStorage base_reg,
181 void GenSelectConst32(RegStorage left_op, RegStorage right_op, ConditionCode code,
202 LIR* OpCmpBranch(ConditionCode cond, RegStorage src1, RegStorage src2, LIR* target) OVERRIDE;
203 LIR* OpCmpImmBranch(ConditionCode cond, RegStorage reg, int check_value, LIR* target) OVERRIDE;
204 LIR* OpCondBranch(ConditionCode cc, LIR* target) OVERRIDE;
205 LIR* OpDecAndBranch(ConditionCode c_code, RegStorage reg, LIR* target) OVERRIDE;
207 LIR* OpIT(ConditionCode cond, const char* guide) OVERRIDE;
218 LIR* OpCondRegReg(OpKind op, ConditionCode cc, RegStorage r_dest, RegStorage r_src) OVERRIDE;
389 ArmConditionCode ArmConditionEncoding(ConditionCode code);
392 void GenSelect(int32_t left, int32_t right, ConditionCode code, RegStorage rs_dest,
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| D | int_arm64.cc | 35 LIR* Arm64Mir2Lir::OpCmpBranch(ConditionCode cond, RegStorage src1, RegStorage src2, LIR* target) { in OpCmpBranch()
40 LIR* Arm64Mir2Lir::OpIT(ConditionCode ccode, const char* guide) { in OpIT()
99 void Arm64Mir2Lir::GenSelect(int32_t true_val, int32_t false_val, ConditionCode ccode, in GenSelect()
183 void Arm64Mir2Lir::GenSelectConst32(RegStorage left_op, RegStorage right_op, ConditionCode code, in GenSelectConst32()
229 ConditionCode ccode = mir->meta.ccode; in GenFusedLongCmpBranch()
268 LIR* Arm64Mir2Lir::OpCmpImmBranch(ConditionCode cond, RegStorage reg, int check_value, in OpCmpImmBranch()
300 LIR* Arm64Mir2Lir::OpCmpMemImmBranch(ConditionCode cond, RegStorage temp_reg, in OpCmpMemImmBranch()
1025 LIR* Arm64Mir2Lir::OpDecAndBranch(ConditionCode c_code, RegStorage reg, LIR* target) { in OpDecAndBranch()
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| D | fp_arm64.cc | 247 ConditionCode ccode = mir->meta.ccode; in GenFusedFPCmpBranch()
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| D | utility_arm64.cc | 545 LIR* Arm64Mir2Lir::OpCondBranch(ConditionCode cc, LIR* target) { in OpCondBranch()
689 LIR* Arm64Mir2Lir::OpCondRegReg(OpKind op, ConditionCode cc, RegStorage r_dest, RegStorage r_src) { in OpCondRegReg()
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| D | target_arm64.cc | 190 ArmConditionCode Arm64Mir2Lir::ArmConditionEncoding(ConditionCode ccode) { in ArmConditionEncoding()
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| /art/compiler/dex/quick/mips/ |
| D | codegen_mips.h | 181 void GenSelectConst32(RegStorage left_op, RegStorage right_op, ConditionCode code,
196 LIR* OpCmpBranch(ConditionCode cond, RegStorage src1, RegStorage src2, LIR* target);
197 LIR* OpCmpImmBranch(ConditionCode cond, RegStorage reg, int check_value, LIR* target);
198 LIR* OpCondBranch(ConditionCode cc, LIR* target);
199 LIR* OpDecAndBranch(ConditionCode c_code, RegStorage reg, LIR* target);
201 LIR* OpIT(ConditionCode cond, const char* guide);
212 LIR* OpCondRegReg(OpKind op, ConditionCode cc, RegStorage r_dest, RegStorage r_src);
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| D | int_mips.cc | 83 LIR* MipsMir2Lir::OpCmpBranch(ConditionCode cond, RegStorage src1, RegStorage src2, LIR* target) { in OpCmpBranch()
149 LIR* MipsMir2Lir::OpCmpImmBranch(ConditionCode cond, RegStorage reg, int check_value, LIR* target) { in OpCmpImmBranch()
280 void MipsMir2Lir::GenSelectConst32(RegStorage left_op, RegStorage right_op, ConditionCode code, in GenSelectConst32()
460 LIR* MipsMir2Lir::OpDecAndBranch(ConditionCode c_code, RegStorage reg, LIR* target) { in OpDecAndBranch()
478 LIR* MipsMir2Lir::OpIT(ConditionCode cond, const char* guide) { in OpIT()
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| D | utility_mips.cc | 536 LIR* MipsMir2Lir::OpCondRegReg(OpKind op, ConditionCode cc, RegStorage r_dest, RegStorage r_src) { in OpCondRegReg()
1040 LIR* MipsMir2Lir::OpCondBranch(ConditionCode cc, LIR* target) { in OpCondBranch()
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| /art/compiler/dex/quick/x86/ |
| D | codegen_x86.h | 271 void GenSelectConst32(RegStorage left_op, RegStorage right_op, ConditionCode code,
295 LIR* OpCmpBranch(ConditionCode cond, RegStorage src1, RegStorage src2, LIR* target) OVERRIDE;
296 LIR* OpCmpImmBranch(ConditionCode cond, RegStorage reg, int check_value, LIR* target) OVERRIDE;
297 LIR* OpCondBranch(ConditionCode cc, LIR* target) OVERRIDE;
298 LIR* OpDecAndBranch(ConditionCode c_code, RegStorage reg, LIR* target) OVERRIDE;
300 LIR* OpIT(ConditionCode cond, const char* guide) OVERRIDE;
311 LIR* OpCondRegReg(OpKind op, ConditionCode cc, RegStorage r_dest, RegStorage r_src) OVERRIDE;
498 int64_t val, ConditionCode ccode);
814 LIR* OpCmpMemImmBranch(ConditionCode cond, RegStorage temp_reg, RegStorage base_reg,
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| D | int_x86.cc | 75 X86ConditionCode X86ConditionEncoding(ConditionCode cond) { in X86ConditionEncoding()
99 LIR* X86Mir2Lir::OpCmpBranch(ConditionCode cond, RegStorage src1, RegStorage src2, LIR* target) { in OpCmpBranch()
108 LIR* X86Mir2Lir::OpCmpImmBranch(ConditionCode cond, RegStorage reg, in OpCmpImmBranch()
212 void X86Mir2Lir::GenSelectConst32(RegStorage left_op, RegStorage right_op, ConditionCode code, in GenSelectConst32()
281 ConditionCode ccode = mir->meta.ccode; in GenSelect()
339 ConditionCode cc = true_zero_case ? NegateComparison(ccode) : ccode; in GenSelect()
392 ConditionCode ccode = mir->meta.ccode; in GenFusedLongCmpBranch()
452 int64_t val, ConditionCode ccode) { in GenFusedLongCmpImmBranch()
979 ConditionCode cc = is_min ? kCondGe : kCondLt; in GenInlinedMinMax()
1019 ConditionCode condition_code = is_min ? kCondGt : kCondLt; in GenInlinedMinMax()
[all …]
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| D | utility_x86.cc | 119 LIR* X86Mir2Lir::OpCondBranch(ConditionCode cc, LIR* target) { in OpCondBranch()
362 LIR* X86Mir2Lir::OpCondRegReg(OpKind op, ConditionCode cc, RegStorage r_dest, RegStorage r_src) { in OpCondRegReg()
945 LIR* X86Mir2Lir::OpCmpMemImmBranch(ConditionCode cond, RegStorage temp_reg, RegStorage base_reg, in OpCmpMemImmBranch()
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| D | x86_lir.h | 734 extern X86ConditionCode X86ConditionEncoding(ConditionCode cond);
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| D | fp_x86.cc | 532 ConditionCode ccode = mir->meta.ccode; in GenFusedFPCmpBranch()
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| /art/compiler/dex/quick/ |
| D | mir_to_lir.h | 674 ConditionCode FlipComparisonOrder(ConditionCode before);
675 ConditionCode NegateComparison(ConditionCode before);
800 void GenDivZeroCheck(ConditionCode c_code);
1136 virtual LIR* OpCmpMemImmBranch(ConditionCode cond, RegStorage temp_reg, RegStorage base_reg,
1363 virtual void GenSelectConst32(RegStorage left_op, RegStorage right_op, ConditionCode code,
1406 virtual LIR* OpCmpBranch(ConditionCode cond, RegStorage src1, RegStorage src2, LIR* target) = 0;
1407 virtual LIR* OpCmpImmBranch(ConditionCode cond, RegStorage reg, int check_value,
1409 virtual LIR* OpCondBranch(ConditionCode cc, LIR* target) = 0;
1410 virtual LIR* OpDecAndBranch(ConditionCode c_code, RegStorage reg, LIR* target) = 0;
1412 virtual LIR* OpIT(ConditionCode cond, const char* guide) = 0;
[all …]
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| D | codegen_util.cc | 997 ConditionCode Mir2Lir::FlipComparisonOrder(ConditionCode before) { in FlipComparisonOrder()
998 ConditionCode res; in FlipComparisonOrder()
1013 ConditionCode Mir2Lir::NegateComparison(ConditionCode before) { in NegateComparison()
1014 ConditionCode res; in NegateComparison()
1257 LIR *Mir2Lir::OpCmpMemImmBranch(ConditionCode cond, RegStorage temp_reg, RegStorage base_reg, in OpCmpMemImmBranch()
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| D | gen_common.cc | 186 void Mir2Lir::GenDivZeroCheck(ConditionCode c_code) { in GenDivZeroCheck()
351 ConditionCode cond; in GenCompareAndBranch()
373 cond = static_cast<ConditionCode>(0); in GenCompareAndBranch()
414 ConditionCode cond; in GenCompareZeroAndBranch()
437 cond = static_cast<ConditionCode>(0); in GenCompareZeroAndBranch()
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| /art/compiler/dex/ |
| D | compiler_enums.h | 452 enum ConditionCode { enum
472 std::ostream& operator<<(std::ostream& os, const ConditionCode& kind);
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| D | mir_graph.h | 344 ConditionCode ccode;
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| D | mir_optimization.cc | 226 static constexpr ConditionCode kIfCcZConditionCodes[] = {
233 static constexpr ConditionCode ConditionCodeForIfCcZ(Instruction::Code opcode) { in ConditionCodeForIfCcZ()
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