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Searched refs:VRegA_22s (Results 1 – 6 of 6) sorted by relevance

/art/runtime/
Ddex_instruction.h272 uint4_t VRegA_22s() const { in VRegA_22s() function
273 return VRegA_22s(Fetch16(0)); in VRegA_22s()
318 uint4_t VRegA_22s(uint16_t inst_data) const;
Ddex_instruction-inl.h71 case k22s: return VRegA_22s(); in VRegA()
149 inline uint4_t Instruction::VRegA_22s(uint16_t inst_data) const { in VRegA_22s() function
Ddex_instruction.cc236 …case k22s: os << StringPrintf("%s v%d, v%d, #%+d", opcode, VRegA_22s(), VRegB_22s(), VRegC_22s())… in DumpString()
/art/runtime/interpreter/
Dinterpreter_goto_table_impl.cc2259 shadow_frame.SetVReg(inst->VRegA_22s(inst_data), in ExecuteGotoImpl()
2266 shadow_frame.SetVReg(inst->VRegA_22s(inst_data), in ExecuteGotoImpl()
2273 shadow_frame.SetVReg(inst->VRegA_22s(inst_data), in ExecuteGotoImpl()
2281 shadow_frame, inst->VRegA_22s(inst_data), shadow_frame.GetVReg(inst->VRegB_22s(inst_data)), in ExecuteGotoImpl()
2289 shadow_frame, inst->VRegA_22s(inst_data), shadow_frame.GetVReg(inst->VRegB_22s(inst_data)), in ExecuteGotoImpl()
2296 shadow_frame.SetVReg(inst->VRegA_22s(inst_data), in ExecuteGotoImpl()
2303 shadow_frame.SetVReg(inst->VRegA_22s(inst_data), in ExecuteGotoImpl()
2310 shadow_frame.SetVReg(inst->VRegA_22s(inst_data), in ExecuteGotoImpl()
Dinterpreter_switch_impl.cc2090 shadow_frame.SetVReg(inst->VRegA_22s(inst_data), in ExecuteSwitchImpl()
2097 shadow_frame.SetVReg(inst->VRegA_22s(inst_data), in ExecuteSwitchImpl()
2104 shadow_frame.SetVReg(inst->VRegA_22s(inst_data), in ExecuteSwitchImpl()
2111 bool success = DoIntDivide(shadow_frame, inst->VRegA_22s(inst_data), in ExecuteSwitchImpl()
2119 bool success = DoIntRemainder(shadow_frame, inst->VRegA_22s(inst_data), in ExecuteSwitchImpl()
2127 shadow_frame.SetVReg(inst->VRegA_22s(inst_data), in ExecuteSwitchImpl()
2134 shadow_frame.SetVReg(inst->VRegA_22s(inst_data), in ExecuteSwitchImpl()
2141 shadow_frame.SetVReg(inst->VRegA_22s(inst_data), in ExecuteSwitchImpl()
/art/runtime/verifier/
Dregister_line.cc316 const uint32_t vregA = is_lit16 ? inst->VRegA_22s() : inst->VRegA_22b(); in CheckLiteralOp()