/art/disassembler/ |
D | disassembler_arm.cc | 252 std::string opcode; in DumpArm() local 260 opcode = "bkpt"; in DumpArm() 267 opcode = (((instruction >> 5) & 1) ? "blx" : "bx"); in DumpArm() 274 opcode = kDataProcessingOperations[op]; in DumpArm() 313 opcode = StringPrintf("%s%s", (l ? "ldr" : "str"), (b ? "b" : "")); in DumpArm() 343 opcode = StringPrintf("%s%c%c", (l ? "ldm" : "stm"), (u ? 'i' : 'd'), (p ? 'b' : 'a')); in DumpArm() 350 opcode = (bl ? "bl" : "b"); in DumpArm() 357 opcode = "???"; in DumpArm() 360 opcode += kConditionCodeNames[cond]; in DumpArm() 361 opcode += suffixes; in DumpArm() [all …]
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/art/compiler/dex/quick/ |
D | mir_to_lir-inl.h | 46 inline LIR* Mir2Lir::RawLIR(DexOffset dalvik_offset, int opcode, int op0, in RawLIR() argument 50 insn->opcode = opcode; in RawLIR() 58 if ((opcode == kPseudoTargetLabel) || (opcode == kPseudoSafepointPC) || in RawLIR() 59 (opcode == kPseudoExportedPC)) { in RawLIR() 71 inline LIR* Mir2Lir::NewLIR0(int opcode) { in NewLIR0() argument 72 DCHECK(IsPseudoLirOp(opcode) || (GetTargetInstFlags(opcode) & NO_OPERAND)) in NewLIR0() 73 << GetTargetInstName(opcode) << " " << opcode << " " in NewLIR0() 76 LIR* insn = RawLIR(current_dalvik_offset_, opcode); in NewLIR0() 81 inline LIR* Mir2Lir::NewLIR1(int opcode, int dest) { in NewLIR1() argument 82 DCHECK(IsPseudoLirOp(opcode) || (GetTargetInstFlags(opcode) & IS_UNARY_OP)) in NewLIR1() [all …]
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D | dex_file_method_inliner.cc | 122 DCHECK(!MIR::DecodedInstruction::IsPseudoMirOp(invoke->dalvikInsn.opcode)); in GetInvokeReg() 123 if (IsInvokeInstructionRange(invoke->dalvikInsn.opcode)) { in GetInvokeReg() 126 DCHECK_EQ(Instruction::FormatOf(invoke->dalvikInsn.opcode), Instruction::k35c); in GetInvokeReg() 133 DCHECK(!MIR::DecodedInstruction::IsPseudoMirOp(invoke->dalvikInsn.opcode)); in WideArgIsInConsecutiveDalvikRegs() 134 return IsInvokeInstructionRange(invoke->dalvikInsn.opcode) || in WideArgIsInConsecutiveDalvikRegs() 537 if (kIntrinsicIsStatic[intrinsic.opcode] != (info->type == kStatic)) { in GenIntrinsic() 541 switch (intrinsic.opcode) { in GenIntrinsic() 618 LOG(FATAL) << "Unexpected intrinsic opcode: " << intrinsic.opcode; in GenIntrinsic() 656 switch (method.opcode) { in GenInline() 678 LOG(FATAL) << "Unexpected inline op: " << method.opcode; in GenInline() [all …]
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/art/compiler/dex/quick/x86/ |
D | utility_x86.cc | 34 int opcode; in OpFpRegCopy() local 39 opcode = kX86MovsdRR; in OpFpRegCopy() 43 opcode = kX86MovssRR; in OpFpRegCopy() 45 opcode = kX86MovdxrRR; in OpFpRegCopy() 49 opcode = kX86MovdrxRR; in OpFpRegCopy() 52 DCHECK_NE((EncodingMap[opcode].flags & IS_BINARY_OP), 0ULL); in OpFpRegCopy() 53 LIR* res = RawLIR(current_dalvik_offset_, opcode, r_dest.GetReg(), r_src.GetReg()); in OpFpRegCopy() 127 X86OpCode opcode = kX86Bkpt; in OpReg() local 129 case kOpNeg: opcode = r_dest_src.Is64Bit() ? kX86Neg64R : kX86Neg32R; break; in OpReg() 130 case kOpNot: opcode = r_dest_src.Is64Bit() ? kX86Not64R : kX86Not32R; break; in OpReg() [all …]
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D | x86_lir.h | 379 #define BinaryOpCode(opcode) \ argument 380 opcode ## 8MR, opcode ## 8AR, opcode ## 8TR, \ 381 opcode ## 8RR, opcode ## 8RM, opcode ## 8RA, opcode ## 8RT, \ 382 opcode ## 8RI, opcode ## 8MI, opcode ## 8AI, opcode ## 8TI, \ 383 opcode ## 16MR, opcode ## 16AR, opcode ## 16TR, \ 384 opcode ## 16RR, opcode ## 16RM, opcode ## 16RA, opcode ## 16RT, \ 385 opcode ## 16RI, opcode ## 16MI, opcode ## 16AI, opcode ## 16TI, \ 386 opcode ## 16RI8, opcode ## 16MI8, opcode ## 16AI8, opcode ## 16TI8, \ 387 opcode ## 32MR, opcode ## 32AR, opcode ## 32TR, \ 388 opcode ## 32RR, opcode ## 32RM, opcode ## 32RA, opcode ## 32RT, \ [all …]
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/art/tools/dexfuzz/src/dexfuzz/program/mutators/ |
D | ValuePrinter.java | 216 Opcode opcode = mInsn.insn.info.opcode; in getInstructionOutputType() local 217 if (opcode == Opcode.CONST_STRING || opcode == Opcode.CONST_STRING_JUMBO) { in getInstructionOutputType() 220 if (opcode == Opcode.IGET_BOOLEAN || opcode == Opcode.SGET_BOOLEAN) { in getInstructionOutputType() 223 if (opcode == Opcode.IGET_BYTE || opcode == Opcode.SGET_BYTE in getInstructionOutputType() 224 || opcode == Opcode.INT_TO_BYTE) { in getInstructionOutputType() 227 if (opcode == Opcode.IGET_CHAR || opcode == Opcode.SGET_CHAR in getInstructionOutputType() 228 || opcode == Opcode.INT_TO_CHAR) { in getInstructionOutputType() 231 if (opcode == Opcode.IGET_SHORT || opcode == Opcode.SGET_SHORT in getInstructionOutputType() 232 || opcode == Opcode.INT_TO_SHORT) { in getInstructionOutputType() 235 if (opcode == Opcode.NEG_INT || opcode == Opcode.NOT_INT in getInstructionOutputType() [all …]
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D | CmpBiasChanger.java | 134 Opcode opcode = mInsn.insn.info.opcode; in getLegalDifferentOpcode() local 135 if (opcode == Opcode.CMPG_DOUBLE) { in getLegalDifferentOpcode() 138 if (opcode == Opcode.CMPL_DOUBLE) { in getLegalDifferentOpcode() 141 if (opcode == Opcode.CMPG_FLOAT) { in getLegalDifferentOpcode() 148 Opcode opcode = mInsn.insn.info.opcode; in isCmpBiasOperation() local 149 if (Opcode.isBetween(opcode, Opcode.CMPL_FLOAT, Opcode.CMPG_DOUBLE)) { in isCmpBiasOperation()
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D | InstructionDuplicator.java | 74 Opcode opcode = oldInsn.insn.info.opcode; in generateMutation() local 76 if (opcode == Opcode.SPARSE_SWITCH || opcode == Opcode.PACKED_SWITCH in generateMutation() 77 || opcode == Opcode.FILL_ARRAY_DATA || oldInsn.insn.justRaw) { in generateMutation()
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/art/runtime/ |
D | dex_instruction_utils.h | 52 constexpr bool IsInstructionReturn(Instruction::Code opcode) { in IsInstructionReturn() argument 53 return Instruction::RETURN_VOID <= opcode && opcode <= Instruction::RETURN_OBJECT; in IsInstructionReturn() 56 constexpr bool IsInstructionInvoke(Instruction::Code opcode) { in IsInstructionInvoke() argument 57 return Instruction::INVOKE_VIRTUAL <= opcode && opcode <= Instruction::INVOKE_INTERFACE_RANGE && in IsInstructionInvoke() 58 opcode != Instruction::RETURN_VOID_NO_BARRIER; in IsInstructionInvoke() 61 constexpr bool IsInstructionQuickInvoke(Instruction::Code opcode) { in IsInstructionQuickInvoke() argument 62 return opcode == Instruction::INVOKE_VIRTUAL_QUICK || in IsInstructionQuickInvoke() 63 opcode == Instruction::INVOKE_VIRTUAL_RANGE_QUICK; in IsInstructionQuickInvoke() 66 constexpr bool IsInstructionInvokeStatic(Instruction::Code opcode) { in IsInstructionInvokeStatic() argument 67 return opcode == Instruction::INVOKE_STATIC || opcode == Instruction::INVOKE_STATIC_RANGE; in IsInstructionInvokeStatic() [all …]
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D | dex_instruction.cc | 63 #define INSTRUCTION_SIZE(opcode, c, p, format, r, i, a, v) \ argument 64 ((opcode == NOP) ? -1 : \ 93 Code opcode = static_cast<Code>(insn & 0xFF); in CanFlowThrough() local 94 return FlagsOf(opcode) & Instruction::kContinue; in CanFlowThrough() 156 const char* opcode = kInstructionNames[Opcode()]; in DumpString() local 158 case k10x: os << opcode; break; in DumpString() 159 case k12x: os << StringPrintf("%s v%d, v%d", opcode, VRegA_12x(), VRegB_12x()); break; in DumpString() 160 case k11n: os << StringPrintf("%s v%d, #%+d", opcode, VRegA_11n(), VRegB_11n()); break; in DumpString() 161 case k11x: os << StringPrintf("%s v%d", opcode, VRegA_11x()); break; in DumpString() 162 case k10t: os << StringPrintf("%s %+d", opcode, VRegA_10t()); break; in DumpString() [all …]
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/art/compiler/dex/quick/arm64/ |
D | utility_arm64.cc | 93 bool opcode_is_wide = IS_WIDE(lir->opcode); in GetLoadStoreSize() 94 A64Opcode opcode = UNWIDE(lir->opcode); in GetLoadStoreSize() local 95 DCHECK(!IsPseudoLirOp(opcode)); in GetLoadStoreSize() 96 const A64EncodingMap *encoder = &EncodingMap[opcode]; in GetLoadStoreSize() 103 uint64_t check_flags = GetTargetInstFlags(lir->opcode); in GetInstructionOffset() 336 bool Arm64Mir2Lir::InexpensiveConstantInt(int32_t value, Instruction::Code opcode) { in InexpensiveConstantInt() argument 337 switch (opcode) { in InexpensiveConstantInt() 420 A64Opcode opcode = LIKELY(low_bits == 0) ? kA64Mov2rr : kA64Mvn2rr; in LoadConstantNoClobber() local 421 res = NewLIR2(opcode, r_dest.GetReg(), rwzr); in LoadConstantNoClobber() 471 A64Opcode opcode = LIKELY(value == 0) ? WIDE(kA64Mov2rr) : WIDE(kA64Mvn2rr); in LoadConstantWide() local [all …]
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/art/compiler/dex/quick/arm/ |
D | utility_arm.cc | 138 bool ArmMir2Lir::InexpensiveConstantInt(int32_t value, Instruction::Code opcode) { in InexpensiveConstantInt() argument 139 switch (opcode) { in InexpensiveConstantInt() 271 ArmOpcode opcode = kThumbBkpt; in OpReg() local 274 opcode = kThumbBlxR; in OpReg() 277 opcode = kThumbBx; in OpReg() 282 return NewLIR1(opcode, r_dest_src.GetReg()); in OpReg() 289 ArmOpcode opcode = kThumbBkpt; in OpRegRegShift() local 292 opcode = (thumb_form) ? kThumbAdcRR : kThumb2AdcRRR; in OpRegRegShift() 295 opcode = (thumb_form) ? kThumbAndRR : kThumb2AndRRR; in OpRegRegShift() 298 opcode = (thumb_form) ? kThumbBicRR : kThumb2BicRRR; in OpRegRegShift() [all …]
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/art/compiler/dex/quick/mips/ |
D | utility_mips.cc | 33 int opcode; in OpFpRegCopy() local 39 opcode = kMipsFmovd; in OpFpRegCopy() 45 opcode = kMips64Dmtc1; in OpFpRegCopy() 49 opcode = kMips64Dmfc1; in OpFpRegCopy() 54 opcode = kMipsFmovs; in OpFpRegCopy() 60 opcode = kMipsMtc1; in OpFpRegCopy() 64 opcode = kMipsMfc1; in OpFpRegCopy() 71 opcode = kMipsFmovd; in OpFpRegCopy() 75 opcode = kMipsFmovs; in OpFpRegCopy() 81 opcode = kMipsMtc1; in OpFpRegCopy() [all …]
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D | assemble_mips.cc | 44 #define ENCODING_MAP(opcode, skeleton, k0, ds, de, k1, s1s, s1e, k2, s2s, s2e, \ argument 47 {k3, k3s, k3e}}, opcode, flags, name, fmt, size} 595 int opcode = lir->opcode; in ConvertShortToLongBranch() local 597 switch (opcode) { in ConvertShortToLongBranch() 604 case kMipsBeq: opcode = kMipsBne; break; in ConvertShortToLongBranch() 605 case kMipsBne: opcode = kMipsBeq; break; in ConvertShortToLongBranch() 606 case kMipsBeqz: opcode = kMipsBnez; break; in ConvertShortToLongBranch() 607 case kMipsBgez: opcode = kMipsBltz; break; in ConvertShortToLongBranch() 608 case kMipsBgtz: opcode = kMipsBlez; break; in ConvertShortToLongBranch() 609 case kMipsBlez: opcode = kMipsBgtz; break; in ConvertShortToLongBranch() [all …]
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D | fp_mips.cc | 26 void MipsMir2Lir::GenArithOpFloat(Instruction::Code opcode, RegLocation rl_dest, in GenArithOpFloat() argument 35 switch (opcode) { in GenArithOpFloat() 63 LOG(FATAL) << "Unexpected opcode: " << opcode; in GenArithOpFloat() 72 void MipsMir2Lir::GenArithOpDouble(Instruction::Code opcode, RegLocation rl_dest, in GenArithOpDouble() argument 77 switch (opcode) { in GenArithOpDouble() 105 LOG(FATAL) << "Unpexpected opcode: " << opcode; in GenArithOpDouble() 132 void MipsMir2Lir::GenConversion(Instruction::Code opcode, RegLocation rl_dest, in GenConversion() argument 136 switch (opcode) { in GenConversion() 168 LOG(FATAL) << "Unexpected opcode: " << opcode; in GenConversion() 208 void MipsMir2Lir::GenCmpFP(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1, in GenCmpFP() argument [all …]
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/art/tools/dexfuzz/src/dexfuzz/rawdex/ |
D | CodeItem.java | 149 Opcode opcode = insn.info.opcode; in incrementIndex() local 152 if (opcode == Opcode.CONST_STRING || opcode == Opcode.CONST_STRING_JUMBO) { in incrementIndex() 160 if (opcode == Opcode.CONST_CLASS in incrementIndex() 161 || opcode == Opcode.CHECK_CAST in incrementIndex() 162 || opcode == Opcode.NEW_INSTANCE in incrementIndex() 163 || opcode == Opcode.FILLED_NEW_ARRAY in incrementIndex() 164 || opcode == Opcode.FILLED_NEW_ARRAY_RANGE) { in incrementIndex() 169 } else if (opcode == Opcode.INSTANCE_OF || opcode == Opcode.NEW_ARRAY) { in incrementIndex() 177 if (Opcode.isBetween(opcode, Opcode.SGET, Opcode.SPUT_SHORT)) { in incrementIndex() 182 } else if (Opcode.isBetween(opcode, Opcode.IGET, Opcode.IPUT_SHORT)) { in incrementIndex() [all …]
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D | OpcodeInfo.java | 27 public final Opcode opcode; field in OpcodeInfo 35 public OpcodeInfo(Opcode opcode, String name, int opcodeValue, AbstractFormat fmt) { in OpcodeInfo() argument 36 this.opcode = opcode; in OpcodeInfo()
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/art/runtime/quick/ |
D | inline_method_analyser.h | 140 InlineMethodOpcode opcode; member 162 static constexpr bool IsInstructionIGet(Instruction::Code opcode) { in IsInstructionIGet() argument 163 return Instruction::IGET <= opcode && opcode <= Instruction::IGET_SHORT; in IsInstructionIGet() 166 static constexpr bool IsInstructionIPut(Instruction::Code opcode) { in IsInstructionIPut() argument 167 return Instruction::IPUT <= opcode && opcode <= Instruction::IPUT_SHORT; in IsInstructionIPut() 170 static constexpr uint16_t IGetVariant(Instruction::Code opcode) { in IGetVariant() argument 171 return opcode - Instruction::IGET; in IGetVariant() 174 static constexpr uint16_t IPutVariant(Instruction::Code opcode) { in IPutVariant() argument 175 return opcode - Instruction::IPUT; in IPutVariant()
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D | inline_method_analyser.cc | 85 Instruction::Code opcode = instruction->Opcode(); in AnalyseMethodCode() local 87 switch (opcode) { in AnalyseMethodCode() 90 method->opcode = kInlineOpNop; in AnalyseMethodCode() 154 result->opcode = kInlineOpReturnArg; in AnalyseReturnMethod() 191 result->opcode = kInlineOpNonWideConst; in AnalyseConstMethod() 202 Instruction::Code opcode = instruction->Opcode(); in AnalyseIGetMethod() local 203 DCHECK(IsInstructionIGet(opcode)); in AnalyseIGetMethod() 207 if (!(return_opcode == Instruction::RETURN_WIDE && opcode == Instruction::IGET_WIDE) && in AnalyseIGetMethod() 208 !(return_opcode == Instruction::RETURN_OBJECT && opcode == Instruction::IGET_OBJECT) && in AnalyseIGetMethod() 209 !(return_opcode == Instruction::RETURN && opcode != Instruction::IGET_WIDE && in AnalyseIGetMethod() [all …]
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/art/compiler/dex/ |
D | local_value_numbering_test.cc | 46 Instruction::Code opcode; member 55 #define DEF_CONST(opcode, reg, value) \ argument 56 { opcode, value, 0u, 0, { }, 1, { reg } } 57 #define DEF_CONST_WIDE(opcode, reg, value) \ argument 58 { opcode, value, 0u, 0, { }, 2, { reg, reg + 1 } } 59 #define DEF_CONST_STRING(opcode, reg, index) \ argument 60 { opcode, index, 0u, 0, { }, 1, { reg } } 61 #define DEF_IGET(opcode, reg, obj, field_info) \ argument 62 { opcode, 0u, field_info, 1, { obj }, 1, { reg } } 63 #define DEF_IGET_WIDE(opcode, reg, obj, field_info) \ argument [all …]
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D | mir_optimization.cc | 77 switch (d_insn->opcode) { in DoConstantPropagation() 149 if ((mir->dalvikInsn.opcode == Instruction::MOVE_RESULT) || in FindMoveResult() 150 (mir->dalvikInsn.opcode == Instruction::MOVE_RESULT_OBJECT) || in FindMoveResult() 151 (mir->dalvikInsn.opcode == Instruction::MOVE_RESULT_WIDE)) { in FindMoveResult() 155 if (MIR::DecodedInstruction::IsPseudoMirOp(mir->dalvikInsn.opcode)) { in FindMoveResult() 189 if (static_cast<int>(mir->dalvikInsn.opcode) == kMirOpPhi) { in FindPhi() 205 switch (mir->dalvikInsn.opcode) { in SelectKind() 233 static constexpr ConditionCode ConditionCodeForIfCcZ(Instruction::Code opcode) { in ConditionCodeForIfCcZ() argument 234 return kIfCcZConditionCodes[opcode - Instruction::IF_EQZ]; in ConditionCodeForIfCcZ() 445 static bool EvaluateBranch(Instruction::Code opcode, int32_t src1, int32_t src2) { in EvaluateBranch() argument [all …]
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D | gvn_dead_code_elimination_test.cc | 62 Instruction::Code opcode; member 94 #define DEF_CONST(bb, opcode, reg, value) \ argument 95 { bb, opcode, value, 0u, 0, { }, 1, { reg } } 96 #define DEF_CONST_WIDE(bb, opcode, reg, value) \ argument 97 { bb, opcode, value, 0u, 0, { }, 2, { reg, reg + 1 } } 98 #define DEF_CONST_STRING(bb, opcode, reg, index) \ argument 99 { bb, opcode, index, 0u, 0, { }, 1, { reg } } 100 #define DEF_IGET(bb, opcode, reg, obj, field_info) \ argument 101 { bb, opcode, 0u, field_info, 1, { obj }, 1, { reg } } 102 #define DEF_IGET_WIDE(bb, opcode, reg, obj, field_info) \ argument [all …]
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D | type_inference_test.cc | 65 Instruction::Code opcode; member 97 #define DEF_CONST(bb, opcode, reg, value) \ argument 98 { bb, opcode, value, 0u, 0, { }, 1, { reg } } 99 #define DEF_CONST_WIDE(bb, opcode, reg, value) \ argument 100 { bb, opcode, value, 0u, 0, { }, 2, { reg, reg + 1 } } 101 #define DEF_CONST_STRING(bb, opcode, reg, index) \ argument 102 { bb, opcode, index, 0u, 0, { }, 1, { reg } } 103 #define DEF_IGET(bb, opcode, reg, obj, field_info) \ argument 104 { bb, opcode, 0u, field_info, 1, { obj }, 1, { reg } } 105 #define DEF_IGET_WIDE(bb, opcode, reg, obj, field_info) \ argument [all …]
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/art/runtime/arch/x86/ |
D | fault_handler_x86.cc | 102 uint8_t opcode = *pc++; in GetInstructionSize() local 113 switch (opcode) { in GetInstructionSize() 134 opcode = *pc++; in GetInstructionSize() 143 if (x86_64 && opcode >= 0x40 && opcode <= 0x4f) { in GetInstructionSize() 144 opcode = *pc++; in GetInstructionSize() 147 if (opcode == 0x0f) { in GetInstructionSize() 150 opcode = *pc++; in GetInstructionSize() 156 switch (opcode) { in GetInstructionSize() 171 switch (opcode) { in GetInstructionSize() 208 VLOG(signals) << "Unhandled x86 instruction with opcode " << static_cast<int>(opcode); in GetInstructionSize()
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/art/tools/dexfuzz/src/dexfuzz/rawdex/formats/ |
D | Format21c.java | 67 if (info.opcode == Opcode.CONST_STRING) { in getPoolIndexKind() 70 if (info.opcode == Opcode.CONST_CLASS in getPoolIndexKind() 71 || info.opcode == Opcode.CHECK_CAST in getPoolIndexKind() 72 || info.opcode == Opcode.NEW_INSTANCE) { in getPoolIndexKind()
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