/art/runtime/arch/arm64/ |
D | memcmp16_arm64.S | 29 #define src2 x1 macro 53 eor tmp1, src1, src2 63 ldr data2, [src2], #8 110 bic src2, src2, #7 115 ldr data2, [src2], #8 135 ldrh data2w, [src2], #2
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/art/test/etc/ |
D | default-build | 54 if [ -d src2 ]; then 55 ${JACK} --output-jack src2.jack src2 78 if [ -d src2 ]; then 80 ${JAVAC} -d classes `find src2 -name '*.java'`
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/art/compiler/dex/quick/ |
D | mir_to_lir-inl.h | 111 inline LIR* Mir2Lir::NewLIR3(int opcode, int dest, int src1, int src2) { in NewLIR3() argument 116 LIR* insn = RawLIR(current_dalvik_offset_, opcode, dest, src1, src2); in NewLIR3() 121 inline LIR* Mir2Lir::NewLIR4(int opcode, int dest, int src1, int src2, int info) { in NewLIR4() argument 126 LIR* insn = RawLIR(current_dalvik_offset_, opcode, dest, src1, src2, info); in NewLIR4() 131 inline LIR* Mir2Lir::NewLIR5(int opcode, int dest, int src1, int src2, int info1, in NewLIR5() argument 137 LIR* insn = RawLIR(current_dalvik_offset_, opcode, dest, src1, src2, info1, info2); in NewLIR5()
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D | mir_to_lir.h | 659 LIR* NewLIR3(int opcode, int dest, int src1, int src2); 660 LIR* NewLIR4(int opcode, int dest, int src1, int src2, int info); 661 LIR* NewLIR5(int opcode, int dest, int src1, int src2, int info1, int info2); 1406 virtual LIR* OpCmpBranch(ConditionCode cond, RegStorage src1, RegStorage src2, LIR* target) = 0;
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/art/test/032-concrete-sub/ |
D | expected.txt | 2 In AbstractBase.doStuff (src2)
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/art/test/003-omnibus-opcodes/ |
D | build | 23 ${JAVAC} -d classes `find src2 -name '*.java'`
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/art/test/ |
D | README.txt | 10 in the "src2" directory are compiled separately but to the same output
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/art/compiler/dex/ |
D | ssa_transformation.cc | 414 const ArenaBitVector* src2) { in ComputeSuccLineIn() argument 416 dest->GetStorageSize() != src2->GetStorageSize() || in ComputeSuccLineIn() 418 dest->IsExpandable() != src2->IsExpandable()) { in ComputeSuccLineIn() 424 dest->GetRawStorage()[idx] |= src1->GetRawStorageWord(idx) & ~(src2->GetRawStorageWord(idx)); in ComputeSuccLineIn()
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D | mir_optimization.cc | 445 static bool EvaluateBranch(Instruction::Code opcode, int32_t src1, int32_t src2) { in EvaluateBranch() argument 448 case Instruction::IF_EQ: is_taken = (src1 == src2); break; in EvaluateBranch() 449 case Instruction::IF_NE: is_taken = (src1 != src2); break; in EvaluateBranch() 450 case Instruction::IF_LT: is_taken = (src1 < src2); break; in EvaluateBranch() 451 case Instruction::IF_GE: is_taken = (src1 >= src2); break; in EvaluateBranch() 452 case Instruction::IF_GT: is_taken = (src1 > src2); break; in EvaluateBranch() 453 case Instruction::IF_LE: is_taken = (src1 <= src2); break; in EvaluateBranch()
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D | gvn_dead_code_elimination_test.cc | 134 #define DEF_PHI2(bb, reg, src1, src2) \ argument 135 { bb, static_cast<Instruction::Code>(kMirOpPhi), 0, 0u, 2u, { src1, src2 }, 1, { reg } } 138 #define DEF_BINOP(bb, opcode, result, src1, src2) \ argument 139 { bb, opcode, 0u, 0u, 2, { src1, src2 }, 1, { result } } 140 #define DEF_BINOP_WIDE(bb, opcode, result, src1, src2) \ argument 141 { bb, opcode, 0u, 0u, 4, { src1, src1 + 1, src2, src2 + 1 }, 2, { result, result + 1 } }
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D | type_inference_test.cc | 139 #define DEF_PHI2(bb, reg, src1, src2) \ argument 140 { bb, static_cast<Instruction::Code>(kMirOpPhi), 0, 0u, 2u, { src1, src2 }, 1, { reg } } 141 #define DEF_BINOP(bb, opcode, result, src1, src2) \ argument 142 { bb, opcode, 0u, 0u, 2, { src1, src2 }, 1, { result } }
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D | global_value_numbering_test.cc | 134 #define DEF_PHI2(bb, reg, src1, src2) \ argument 135 { bb, static_cast<Instruction::Code>(kMirOpPhi), 0, 0u, 2u, { src1, src2 }, 1, { reg } } 136 #define DEF_BINOP(bb, opcode, result, src1, src2) \ argument 137 { bb, opcode, 0u, 0u, 2, { src1, src2 }, 1, { result } }
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D | mir_graph.h | 1279 const ArenaBitVector* src2);
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/art/runtime/base/ |
D | bit_vector.h | 171 void Intersect(const BitVector* src2);
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/art/compiler/dex/quick/mips/ |
D | int_mips.cc | 83 LIR* MipsMir2Lir::OpCmpBranch(ConditionCode cond, RegStorage src1, RegStorage src2, LIR* target) { in OpCmpBranch() argument 134 branch = NewLIR2(br_op, src1.GetReg(), src2.GetReg()); in OpCmpBranch() 138 NewLIR3(slt_op, t_reg.GetReg(), src2.GetReg(), src1.GetReg()); in OpCmpBranch() 140 NewLIR3(slt_op, t_reg.GetReg(), src1.GetReg(), src2.GetReg()); in OpCmpBranch()
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D | codegen_mips.h | 196 LIR* OpCmpBranch(ConditionCode cond, RegStorage src1, RegStorage src2, LIR* target);
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/art/compiler/dex/quick/arm/ |
D | codegen_arm.h | 198 LIR* OpCmpBranch(ConditionCode cond, RegStorage src1, RegStorage src2, LIR* target);
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D | int_arm.cc | 35 LIR* ArmMir2Lir::OpCmpBranch(ConditionCode cond, RegStorage src1, RegStorage src2, LIR* target) { in OpCmpBranch() argument 36 OpRegReg(kOpCmp, src1, src2); in OpCmpBranch()
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/art/compiler/dex/quick/arm64/ |
D | codegen_arm64.h | 202 LIR* OpCmpBranch(ConditionCode cond, RegStorage src1, RegStorage src2, LIR* target) OVERRIDE;
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D | int_arm64.cc | 35 LIR* Arm64Mir2Lir::OpCmpBranch(ConditionCode cond, RegStorage src1, RegStorage src2, LIR* target) { in OpCmpBranch() argument 36 OpRegReg(kOpCmp, src1, src2); in OpCmpBranch()
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/art/compiler/dex/quick/x86/ |
D | codegen_x86.h | 295 LIR* OpCmpBranch(ConditionCode cond, RegStorage src1, RegStorage src2, LIR* target) OVERRIDE;
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D | int_x86.cc | 99 LIR* X86Mir2Lir::OpCmpBranch(ConditionCode cond, RegStorage src1, RegStorage src2, LIR* target) { in OpCmpBranch() argument 100 NewLIR2(src1.Is64Bit() ? kX86Cmp64RR : kX86Cmp32RR, src1.GetReg(), src2.GetReg()); in OpCmpBranch()
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/art/runtime/ |
D | debugger.cc | 1256 const uint16_t* src2 = reinterpret_cast<uint16_t*>(a->GetRawData(sizeof(uint16_t), 0)); in OutputArray() local 1257 for (int i = 0; i < count; ++i) JDWP::Write2BE(&dst, src2[offset + i]); in OutputArray()
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