| /external/llvm/lib/Target/Mips/ |
| D | MipsAnalyzeImmediate.cpp | 32 AddInstr(SeqLs, Inst(ADDiu, Imm & 0xffffULL)); in GetInstSeqLsADDiu()
58 AddInstr(SeqLs, Inst(ADDiu, MaskedImm)); in GetInstSeqLs()
89 if ((Seq.size() < 2) || (Seq[0].Opc != ADDiu) || in ReplaceADDiuSLLWithLUi()
131 ADDiu = Mips::ADDiu; in Analyze()
136 ADDiu = Mips::DADDiu; in Analyze()
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| D | MipsSERegisterInfo.cpp | 170 unsigned ADDiu = isN64 ? Mips::DADDiu : Mips::ADDiu; in eliminateFI() local
178 BuildMI(MBB, II, DL, TII.get(ADDiu), Reg).addReg(FrameReg).addImm(Offset); in eliminateFI()
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| D | MipsInstrInfo.td | 115 // target constant nodes that would otherwise remain unchanged with ADDiu
1121 def ADDiu : MMRel, ArithLogicI<"addiu", simm16, GPR32Opnd, II_ADDIU, immSExt16,
1549 (ADDiu GPR32Opnd:$rs, GPR32Opnd:$rt, simm16:$imm), 0>;
1551 (ADDiu GPR32Opnd:$rs, GPR32Opnd:$rs, simm16:$imm), 0>;
1632 (ADDiu GPR32Opnd:$rd, GPR32Opnd:$rs,
1634 def : MipsInstAlias<"subu $rs, $imm", (ADDiu GPR32Opnd:$rs, GPR32Opnd:$rs,
1682 (ADDiu ZERO, imm:$in)>;
1700 (ADDiu GPR32:$src, imm:$imm)>;
1734 def : MipsPat<(MipsLo tglobaladdr:$in), (ADDiu ZERO, tglobaladdr:$in)>;
1735 def : MipsPat<(MipsLo tblockaddress:$in), (ADDiu ZERO, tblockaddress:$in)>;
[all …]
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| D | MipsAnalyzeImmediate.h | 58 unsigned ADDiu, ORi, SLL, LUi; variable
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| D | MipsLongBranch.cpp | 296 BuildMI(*LongBrMBB, Pos, DL, TII->get(Mips::ADDiu), Mips::SP) in expandToLongBranch()
336 .append(BuildMI(*MF, DL, TII->get(Mips::ADDiu), Mips::SP) in expandToLongBranch()
340 BuildMI(*BalTgtMBB, Pos, DL, TII->get(Mips::ADDiu), Mips::SP) in expandToLongBranch()
446 BuildMI(MBB, I, DL, TII->get(Mips::ADDiu), Mips::V0) in emitGPDisp()
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| D | MipsSEInstrInfo.cpp | 365 unsigned ADDiu = STI.isABI_N64() ? Mips::DADDiu : Mips::ADDiu; in adjustStackPtr() local
371 BuildMI(MBB, I, DL, get(ADDiu), SP).addReg(SP).addImm(Amount); in adjustStackPtr()
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| D | MipsMCInstLower.cpp | 203 lowerLongBranchADDiu(MI, OutMI, Mips::ADDiu, in lowerLongBranch()
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| D | MipsSEISelDAGToDAG.cpp | 91 if ((MI.getOpcode() == Mips::ADDiu) && in replaceUsesWithZeroReg()
167 BuildMI(MBB, I, DL, TII.get(Mips::ADDiu), GlobalBaseReg).addReg(V0) in initGlobalBaseReg()
183 BuildMI(MBB, I, DL, TII.get(Mips::ADDiu), GlobalBaseReg).addReg(V1) in initGlobalBaseReg()
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| D | MipsFastISel.cpp | 273 unsigned Opc = Mips::ADDiu; in materialize32BitInt()
332 emitInst(Mips::ADDiu, TempReg) in materializeGV()
604 emitInst(Mips::ADDiu, RegWithZero).addReg(Mips::ZERO).addImm(0); in emitCmp()
605 emitInst(Mips::ADDiu, RegWithOne).addReg(Mips::ZERO).addImm(1); in emitCmp()
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| D | MipsSEISelLowering.cpp | 2777 BuildMI(*FBB, FBB->end(), DL, TII->get(Mips::ADDiu), VR2) in emitBPOSGE32()
2783 BuildMI(*TBB, TBB->end(), DL, TII->get(Mips::ADDiu), VR1) in emitBPOSGE32()
2844 BuildMI(*FBB, FBB->end(), DL, TII->get(Mips::ADDiu), RD1) in emitMSACBranchPseudo()
2850 BuildMI(*TBB, TBB->end(), DL, TII->get(Mips::ADDiu), RD2) in emitMSACBranchPseudo()
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| D | MipsDSPInstrInfo.td | 1340 (ValTy (COPY_TO_REGCLASS (ADDiu ZERO, -1), DSPR)),
1348 (ValTy (COPY_TO_REGCLASS (ADDiu ZERO, -1), DSPR))))>;
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| D | MipsISelLowering.cpp | 1209 BuildMI(BB, DL, TII->get(Mips::ADDiu), MaskLSB2) in emitAtomicBinaryPartword()
1451 BuildMI(BB, DL, TII->get(Mips::ADDiu), MaskLSB2) in emitAtomicCmpSwapPartword()
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| /external/llvm/lib/Target/Mips/MCTargetDesc/ |
| D | MipsTargetStreamer.cpp | 708 TmpInst.setOpcode(Mips::ADDiu); in emitDirectiveCpLoad()
768 Inst.setOpcode(Mips::ADDiu); in emitDirectiveCpsetup()
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| /external/llvm/lib/Target/Mips/AsmParser/ |
| D | MipsAsmParser.cpp | 1730 tmpInst.setOpcode(Mips::ADDiu); in expandLoadImm()
1821 tmpInst.setOpcode(Mips::ADDiu); in expandLoadAddressReg()
1868 tmpInst.setOpcode(Mips::ADDiu); in expandLoadAddressImm()
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