Searched refs:DDIVU (Results 1 – 9 of 9) sorted by relevance
| /external/valgrind/none/tests/mips64/ |
| D | arithmetic_instruction.c | 9 DDIV, DDIVU, DIV, DIVU, enumerator
144 case DDIVU: in main()
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| /external/v8/src/mips64/ |
| D | constants-mips64.cc | 248 case DDIVU: in InstructionType()
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| D | constants-mips64.h | 378 DDIVU = ((3 << 3) + 7), enumerator
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| D | disasm-mips64.cc | 840 case DDIVU: // @Mips64r6 == D_DIV_MOD_U. in DecodeTypeRegister()
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| D | simulator-mips64.cc | 2204 case DDIVU: in ConfigureTypeRegister()
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| D | assembler-mips64.cc | 1604 GenInstrRegister(SPECIAL, rs, rt, zero_reg, 0, DDIVU); in ddivu()
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| /external/llvm/lib/Target/Mips/ |
| D | Mips64r6InstrInfo.td | 92 def DDIVU : DDIVU_ENC, DDIVU_DESC, ISA_MIPS64R6;
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| D | MipsISelLowering.cpp | 994 case Mips::DDIVU: in EmitInstrWithCustomInserter()
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| /external/pcre/dist/sljit/ |
| D | sljitNativeMIPS_common.c | 124 #define DDIVU (HI(0) | LO(31)) macro
1082 …FAIL_IF(push_inst(compiler, (op == SLJIT_UDIV ? DDIVU : DDIV) | S(SLJIT_R0) | T(SLJIT_R1), MOVABLE… in sljit_emit_op0()
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