Searched refs:DSRL (Results 1 – 11 of 11) sorted by relevance
| /external/llvm/test/CodeGen/Mips/ |
| D | fcopysign-f32-f64.ll | 15 ; 64-DAG: dsrl $[[DSRL:[0-9]+]], ${{[0-9]+}}, 63
16 ; 64-DAG: sll $[[SLL0:[0-9]+]], $[[DSRL]], 0
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| /external/valgrind/none/tests/mips64/ |
| D | shift_instructions.c | 8 DSRAV, DSRL, DSRL32, DSRLV, enumerator
114 case DSRL: in main()
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| /external/v8/src/mips64/ |
| D | constants-mips64.cc | 228 case DSRL: in InstructionType()
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| D | constants-mips64.h | 406 DSRL = ((7 << 3) + 2), enumerator
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| D | disasm-mips64.cc | 700 case DSRL: in DecodeTypeRegister()
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| D | assembler-mips64.cc | 1730 GenInstrRegister(SPECIAL, zero_reg, rt, rd, sa, DSRL); in dsrl()
1742 | (rd.code() << kRdShift) | (sa << kSaShift) | DSRL; in drotr()
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| D | simulator-mips64.cc | 2017 case DSRL: in ConfigureTypeRegister()
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| /external/llvm/lib/Target/Mips/MCTargetDesc/ |
| D | MipsMCCodeEmitter.cpp | 71 case Mips::DSRL: in LowerLargeShift()
156 case Mips::DSRL: in EncodeInstruction()
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| /external/llvm/lib/Target/Mips/ |
| D | Mips64InstrInfo.td | 147 def DSRL : shift_rotate_imm<"dsrl", uimm6, GPR64Opnd, II_DSRL, srl, immZExt6>,
507 def : MipsPat<(i64 (zext GPR32:$src)), (DSRL (DSLL64_32 GPR32:$src), 32)>;
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| /external/pcre/dist/sljit/ |
| D | sljitNativeMIPS_64.c | 427 EMIT_SHIFT(DSRL, DSRL32, SRL, DSRLV, SRLV); in emit_single_op()
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| D | sljitNativeMIPS_common.c | 136 #define DSRL (HI(0) | LO(58)) macro
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