Searched refs:DivOpc (Results 1 – 2 of 2) sorted by relevance
| /external/llvm/lib/Target/AArch64/ |
| D | AArch64FastISel.cpp | 4450 unsigned DivOpc; in selectRem() local
4456 DivOpc = Is64bit ? AArch64::SDIVXr : AArch64::SDIVWr; in selectRem()
4459 DivOpc = Is64bit ? AArch64::UDIVXr : AArch64::UDIVWr; in selectRem()
4475 unsigned QuotReg = fastEmitInst_rr(DivOpc, RC, Src0Reg, /*IsKill=*/false, in selectRem()
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | LegalizeDAG.cpp | 3499 unsigned DivOpc = isSigned ? ISD::SDIV : ISD::UDIV; in ExpandNode() local
3506 !TLI.isOperationLegalOrCustom(DivOpc, Node->getValueType(0)) && in ExpandNode()
3510 } else if (TLI.isOperationLegalOrCustom(DivOpc, VT)) { in ExpandNode()
3512 Tmp1 = DAG.getNode(DivOpc, dl, VT, Tmp2, Tmp3); in ExpandNode()
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